Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim
{"title":"Impact of die partitioning on reliability and yield of 3D DRAM","authors":"Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim","doi":"10.1109/IITC.2014.6831841","DOIUrl":null,"url":null,"abstract":"In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.