Impact of die partitioning on reliability and yield of 3D DRAM

Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim
{"title":"Impact of die partitioning on reliability and yield of 3D DRAM","authors":"Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim","doi":"10.1109/IITC.2014.6831841","DOIUrl":null,"url":null,"abstract":"In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"34 1","pages":"389-392"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. In cell/logic-mixed partitioning, each die contains DRAM cells and peripheral logic components except for the last one that contains I/O logic. In our cell/logic-split style, each die contains DRAM cells and small amount of logic except the bottom die that is all logic including peripheral modules and I/O cells. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield.
晶片分割对3D DRAM可靠性及良率的影响
在本文中,我们对采用单元/逻辑混合和单元/逻辑分裂两种实用的芯片划分方式构建的3D SDRAM设计的可靠性和良率进行了比较研究。在单元/逻辑混合分区中,除了最后一个包含I/O逻辑的芯片外,每个芯片都包含DRAM单元和外围逻辑组件。在我们的单元/逻辑分裂风格中,每个模块包含DRAM单元和少量逻辑,除了底部的模块是所有逻辑,包括外围模块和I/O单元。我们的模拟和分析结果在面积、TSV计数、可靠性、功率、性能和良率方面提供了有用的设计权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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