P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet
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3D sequential integration opportunities and technology optimization
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.
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