3D顺序集成机会和技术优化

P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet
{"title":"3D顺序集成机会和技术优化","authors":"P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet","doi":"10.1109/IITC.2014.6831837","DOIUrl":null,"url":null,"abstract":"Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"45 1","pages":"373-376"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":"{\"title\":\"3D sequential integration opportunities and technology optimization\",\"authors\":\"P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet\",\"doi\":\"10.1109/IITC.2014.6831837\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.\",\"PeriodicalId\":6823,\"journal\":{\"name\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"volume\":\"45 1\",\"pages\":\"373-376\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"43\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2014.6831837\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 43

摘要

与基于tsv的3D集成电路相比,单片或顺序3D集成电路呈现出垂直维度的“真正”优势,因为堆叠层可以在晶体管尺度上连接。该技术的高通用性通过几个需要小3D接触间距的例子得到了证明。与平面技术相比,单片3D可以在不缩放晶体管技术节点的情况下实现面积和性能的大幅增加。本文总结了这一概念的技术挑战:它提供了获得高性能低温顶部晶体管同时保持底部MOSFET完整性的潜在解决方案的一般概述。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
3D sequential integration opportunities and technology optimization
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信