T. Min, Z. Tokei, G. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, Kaidong Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, S. Mertens
{"title":"Interconnects scaling challenge for sub-20nm spin torque transfer magnetic random access memory technology","authors":"T. Min, Z. Tokei, G. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, Kaidong Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, S. Mertens","doi":"10.1109/IITC.2014.6831830","DOIUrl":null,"url":null,"abstract":"The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"209 1","pages":"341-344"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.