2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Fan-out ultrasound transducer array in substrate","authors":"Yao Lu, L. Wan","doi":"10.1109/ectc32862.2020.00079","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00079","url":null,"abstract":"The idea that employs an advanced package that combines Embedded Substrate Level Package with Fan-out Substrate Level Package is proposed to package high-density and high-frequency ultrasound transducer array. We successfully verified the process principle. The material of the sample array is lead zirconated titanite piezoelectric ceramic and silicon dummy chip, which total size of arrays is 5000μm× 5000μm×140μm. Arrays are divided into 50×50 elements. Each element size was 70μm × 70 μm×140μm. The kerf between two adjacent array elements is 30μm. We successfully fan out the signal trace of two 1×44 linear arrays in the 50×50 area array using a single-layer re-distribution layer. The impedance curve was measured on the impedance meter. The blind via diameter on the linear array is 30μm, and the line/spacing is 50μm/50μm. We try to fan out a 4×16 planar array in the 50×50 planar array using a single-layer re-distribution layer. The blind via diameter on the planar array is 20μm, and the line width and spacing are 20μm/15μm. However, some questions are leading to the low yield of this process. We analyze the reasons for the low yield.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"33 1","pages":"451-460"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88187637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Frequency Characteristics of Glass Interposer","authors":"Masaya Tanaka, S. Kuramochi, Takahiro Tai, Y. Sato, N. Kidera","doi":"10.1109/ECTC32862.2020.00100","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00100","url":null,"abstract":"As electronic product becomes smaller and lighter with an increasing number of functions. The demand for high density and high integration becomes stronger. The major engineering requirements for 5G and beyond are low loss, precision manufacturing and low cost. Because of the shortwave length, extreme attenuation and low-cost requirements, the holy grail in the industry is ultra-miniaturized mm-wave structures. To achieve high-speed 5G communication standards, miniaturization and short signal pathways are required. This can only be achieved by designing and demonstrating advanced through quartz via (TQV) substrates and multi-layer RDL’s. To demonstrate the performance of quartz glass as a substrate material, we will build interposers with fine pitch TQV with metallization coupled with double sided routing distribution layers utilizing low loss dielectric polymer layers. This paper will model high frequency characteristics for 2.5D high speed applications. We will also demonstrate quartz glass is the ideal candidate for the emerging mm-wave antenna technologies for 5G and beyond.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"601-610"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87156467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tri-axis Polarized Loop Antenna for mmWave Wireless Inter/intra Chip Communications","authors":"Hae-in Kim, Renuka Bowrothu, Y. Yoon","doi":"10.1109/ectc32862.2020.00293","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00293","url":null,"abstract":"We present a tri-axis polarized dual loop antenna for inter/intra chip/board wireless communications in a 3D system-in-package (SiP). The advantages of the presented antenna are as follows: 1) the loop antenna enables inter/intra chip/board communications in all three directions along x, y, and z-axis at 77 GHz; 2) also, the two loops can be designed to produce rather arbitrary main radiation robes without being orthogonal each other, which facilitates improved antenna efficiency in desirable communication directions; 3) since two vertical via holes are the part of the design, this loop antenna can be easily integrated with any through-substrate via structures in a compact footprint of 1.1 mm2. Analytical study for the radiation patterns is carried out and the resultant radiation patterns are compared to simulated ones with High Frequency Structure Simulator (HFSS, ANSYS Inc.). The simulated efficiency and antenna peak gain are 94 % and 3.14 dBi, respectively. A prototype is fabricated on a 254 μm thick RT duroid 5880 substrate using microfabrication and milling machines. Antenna performance is characterized using vector network analyzer with scattering parameters.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"98 1","pages":"1875-1880"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73066712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Irregular Bumps Design Planning for Modern Ball Grid Array Packages","authors":"Hsin-Yu Chang, Hung-Ming Chen, Yun-Chih Kuo, Hsien-Ting Tsai, S. Chen, Jyun-Ru Jiang, Ya-Ying Chien, Yu-Yang Chen","doi":"10.1109/ectc32862.2020.00287","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00287","url":null,"abstract":"In modern flip-chip packages, bumps are often placed irregularly due to different design needs. It costs a great amount of time and manual effort to generate substrate routing from bumps through vias to package balls. Moreover, any single model in prior works could not be simultaneously applied between bumps, vias and balls. In this work, we propose a unified flow network model to formulate the 2-layer substrate routing problem on irregular package structure. We present a renovated bump model that can handle irregular bump plans, filling the gap/insufficiency in existing models. With our methodology, signal assignment on vias and balls, and substrate routing on two layers can be obtained at the same time. We also present an iterative optimization technique to further improve wire congestion. Our results show that the proposed method completes via and ball assignment efficiently, and obtain 100% routability while improving 16.45% in wirelength, compared with manual design in real industrial cases.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"40 1","pages":"1838-1843"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81160269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-brightness displays made with micro-transfer printed flip-chip microLEDs","authors":"C. Bower, S. Bonafede, B. Raymond, A. Pearson, C. Prevatte, T. Weeks, E. Radauscher, E. Vick, C. Verreen, B. Krongard, M. Meitl","doi":"10.1109/ectc32862.2020.00040","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00040","url":null,"abstract":"The incumbent flat-panel technologies, liquid crystal display (LCD) and organic light-emitting diode display (OLED), are ill-suited to produce compact, efficient, and robust high-brightness displays. LCDs are very inefficient, only a small fraction (~5%) of the generated light exits the display. To achieve highbrightness LCDs, practitioners create extremely bright back-light units using inorganic LEDs which require expensive and unreliable active cooling solutions. OLEDs use organic molecules to form light emitting diodes within each display pixel. The lifetime of the organic light emitters is inversely proportional with the display brightness; therefore, OLEDs are not suitable for highbrightness applications. In sharp contrast, inorganic LEDs made using wafer-level semiconductor technology are long-lived, even when operating at high luminance. Displays that use inorganic LEDs as the light-emitters within each display pixel already dominate the giant video walls that increasingly decorate our highways and streetscapes. Today, there are many efforts around the world aimed at making highly miniaturized inorganic LEDs, called microLEDs, and developing methods to transfer those microLEDs from their native substrate to the destination display substrate. Effective techniques to produce microLED displays must have the capability to quickly and accurately transfer millions of microscale devices and are called \"mass transfer\" technologies. Micro-transfer-printing using elastomer stamps is one such \"mass transfer\" technology that has been used to produce prototype microLED displays. Here, we will describe how micro-transfer-printing combined with wafer-level packaging techniques can produce highbrightness displays. We will provide fabrication details and characterization results of various 5.1\" 70 PPI microLED displays. In one example, we produced a monochrome green display using 8 μm x 15 μm flip-chip InGaN microLEDs with a maximum brightness in excess of 30,000 nits. We will highlight application opportunities and remaining challenges for high-brightness displays using microLEDs.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"58 1","pages":"175-181"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81588908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strategies relating to CMP for die to wafer interconnects utilizing hybrid direct bonding","authors":"J. S. Sierra Suarez, John P. Mudrick, Crystal C. Sennett, T. Friedmann, Shawn Arterburn, M. Jordan, L. Caravello, J. Gutierrez, M. David Henry","doi":"10.1109/ectc32862.2020.00304","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00304","url":null,"abstract":"In this study we examine a split-foundry multilevel application specific integrated circuit (ASIC) Si-interposer and die bonded using the direct bond interface (DBI) process, in addition to shortloop vehicles. The designs have been subject to relaxed pattern density rules, and exhibit chemical mechanical planarization (CMP) systematic process issues of varying degrees. We find that the interconnect formation is robust against moderate dielectric thickness variation, as well as a moderate degree of copper corrosion. We discuss and demonstrate various CMP methods which have a clear and repeatable impact. Pattern density effects and defectivity on the bond quality are examined using focused ion beam scanning electron microscope (FIB-SEM) images at the feature scale (sub 100 um) and intra-die scale (few mm). Impact to the CMP performance, including plug recess, and defectivity are discussed.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1950-1956"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83948450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Visualization and Modeling of Microstructural Evolution in SAC305 BGA Joints during Extreme High Temperature Aging","authors":"KM Rafidh Hassan, M. Alam, Jing Wu, J. Suhling, P. Lall","doi":"10.1109/ectc32862.2020.00296","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00296","url":null,"abstract":"Solder joints provide mechanical support, electrical and thermal interconnection between packaging levels in microelectronics assembly systems. Proper functioning of these interconnections and the reliability of the electronic packages depend largely on the mechanical properties of the solder joints. Lead free solders are common as interconnects in electronic packaging due to their relatively high melting point, attractive mechanical properties, thermal cycling reliability, and environment friendly chemical properties. However, environmental conditions, such as, operating temperature, aging temperature, and aging time significantly affect these properties due to the microstructural evolution of the solder that occurs during aging. Moreover, electronic devices, sometimes experience harsh environment applications including well drilling, geothermal energy, automotive power electronics, and aerospace engines, where solders are exposed to very high temperatures from T = 125-200 °C. Mechanical properties as well as microstructural study of lead free solders at elevated temperatures are limited in literature. Previous investigations on the microstructural evolution mainly emphasized on aging at temperatures up to 125 °C. In addition, those studies were limited on investigating the coarsening of Ag3Sn IMC particles within the beta-Sn matrix.In this work, the microstructural evolution of SAC305 (96.5Sn-3.0Ag-0.5Cu) BGA joints were investigated for different aging conditions utilizing Scanning Electron Microscopy (SEM). In particular, our approach has been to monitor aging induced microstructural changes occurring within fixed regions in selected lead free solder joints, and to create time-lapse imagery of the microstructure evolution. Aging was performed at T = 150 °C for several durations up to 20 days, and the topography of the microstructure of a fixed region was captured using the SEM system. This process generated several images of the microstructure as the aging progressed. We have also explored the Mechanical behavior, and aging effects of SAC305 solder joints at extreme high testing temperatures of T = 150 °C using the method of nanoindentation. To study the aging effects, solder joints were preconditioned for 0, 1, 5, 10, and 30 days at T = 125 °C in a box oven. Nanoindentation testing was then performed on the aged specimens at a test temperature of T = 150 °C to extract the elastic modulus, hardness, and creep performance of the aged material.As expected, the analysis of the evolving SAC305 BGA microstructure showed a significant amount of diffusion of silver and copper in the beta-tin matrix during aging. In addition, the growth of the copper-tin layer at the solder joint and copper pad interface at the PCB side has been visualized, and then measured as a function of aging time and temperature. Quantitative analysis of the evolving microstructure showed that the particles coalesced during aging leading to a decrease in the total number of par","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1894-1903"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82933086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct Bonding of GaN to Diamond Substrate at Room Temperature","authors":"T. Suga, F. Mu","doi":"10.1109/ECTC32862.2020.00210","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00210","url":null,"abstract":"GaN-diamond integration is being paid far more attention to realize a better thermal management of GaN-HEMT device GaN-HEMT device with the increase of the requirements on high power density and high reliability. Although growth method has been widely investigated, novel bonding method bring new possibility to realize GaN-diamond integration without traditional problems. This paper reviewed the previous bonding researches for GaN-diamond integration.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"125 4 1","pages":"1328-1331"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80494253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Facile Preparation of Cu-Ag Micro-Nano Composite Paste for High Power Device Packaging","authors":"Jiaxin Liu, Yun Mou, Yang Peng, Mingxiang Chen","doi":"10.1109/ECTC32862.2020.00124","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00124","url":null,"abstract":"In this paper, a novel Cu-Ag micro-nano composite particle (MNCP) paste was prepared, and a low temperature Cu- Cu bonding with high sheer strength was obtained. The microstructures and morphologies of the Cu-Ag MNCPs were systematically investigated. The surface chemical compositions of the composite particles displayed a little oxidized phenomenon, which could be reduced during sintering and bonding. After sintering at 275°C for 30 min under a low pressure, a sheer strength Cu-Cu bonding joint of 32.7 MPa was achieved. The fracture and cross-sectional microstructures of bonded joints exhibited obvious ductile characteristics and compact structure. These results manifested the Cu-Ag MNCPs are promising materials to fulfill the requirements of die-attach materials for high power device packaging.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"755-761"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89844147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromechanical finite element analysis for designed low-frequency MEMS piezoelectric vibration energy harvester","authors":"Ling Xu, Shengrui Zhou, Ying Xiang, Yinglin Yang","doi":"10.1109/ectc32862.2020.00327","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00327","url":null,"abstract":"This work presents an electromechanical finite element analysis for a proposed MEMS piezoelectric vibration energy harvester. The structure of the MEMS energy harvester consists of a basic cantilever beam with a clamped end mass and a spring net which can enhance the reliability of the device. Aluminum nitride thin film is applied as the piezoelectric function material. The proposed MEMS device is also fabricated, packaged and characterized to determine its performance. The spring net structure design is proven to increase the yield of the MEMS energy harvester chips during transportation. Three dimensional electromechanical finite element model coupled the solid mechanics physics and electrostatics physics is built to simulate the piezoelectric effect. The simulated results and the experimental measured data are in close agreement, which verified the prediction of the finite element model. The validation of the model indicate that the finite model can instruct the design of an ideal MEMS piezoelectric device in short period at a low cost.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"2112-2117"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90354787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}