2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献_第8页

Tri-axis Polarized Loop Antenna for mmWave Wireless Inter/intra Chip Communications 用于毫米波无线芯片间/芯片内通信的三轴极化环形天线

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00293

Hae-in Kim, Renuka Bowrothu, Y. Yoon

{"title":"Tri-axis Polarized Loop Antenna for mmWave Wireless Inter/intra Chip Communications","authors":"Hae-in Kim, Renuka Bowrothu, Y. Yoon","doi":"10.1109/ectc32862.2020.00293","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00293","url":null,"abstract":"We present a tri-axis polarized dual loop antenna for inter/intra chip/board wireless communications in a 3D system-in-package (SiP). The advantages of the presented antenna are as follows: 1) the loop antenna enables inter/intra chip/board communications in all three directions along x, y, and z-axis at 77 GHz; 2) also, the two loops can be designed to produce rather arbitrary main radiation robes without being orthogonal each other, which facilitates improved antenna efficiency in desirable communication directions; 3) since two vertical via holes are the part of the design, this loop antenna can be easily integrated with any through-substrate via structures in a compact footprint of 1.1 mm2. Analytical study for the radiation patterns is carried out and the resultant radiation patterns are compared to simulated ones with High Frequency Structure Simulator (HFSS, ANSYS Inc.). The simulated efficiency and antenna peak gain are 94 % and 3.14 dBi, respectively. A prototype is fabricated on a 254 μm thick RT duroid 5880 substrate using microfabrication and milling machines. Antenna performance is characterized using vector network analyzer with scattering parameters.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"98 1","pages":"1875-1880"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73066712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Defect Localization in Through-Si-Interposer Based 2.5D ICs 基于si - interposer的2.5D集成电路缺陷定位

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ECTC32862.2020.00189

Sajay Bhuvanendran Nair Gourikutty, Yew Meng Chow, J. Alton, Ratan Bhimrao Umralkar, Haonan Bai, Kok Keng Chua, S. Bhattacharya

{"title":"Defect Localization in Through-Si-Interposer Based 2.5D ICs","authors":"Sajay Bhuvanendran Nair Gourikutty, Yew Meng Chow, J. Alton, Ratan Bhimrao Umralkar, Haonan Bai, Kok Keng Chua, S. Bhattacharya","doi":"10.1109/ECTC32862.2020.00189","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00189","url":null,"abstract":"Advanced packaging solutions using Through Silicon Interposers (TSI) are an attractive option to create 2.5D ICs. In many applications such as GPU and FPGA, 2.5D ICs can overcome the power, performance, and form-factor limitations of traditional IC packages. Investigating yield-loss and reliability mechanisms of such packages is made particularly challenging by the multitude of possible failure locations such as in TSV, micro-bumps, underfill, solder ball joints and RDL layers. Existing electrical and physical failure analysis tools do not have adequate resolution to accurately localize the failure in 2.5D IC. In this paper, we present a non-destructive methodology to carry out the failure analysis by localizing the defects which are entirely internal to the package and inaccessible from the exterior. In a through silicon interposer based FPGA package, a short failure has been successfully located with an accuracy of less than 10μm without the need for any sample preparation. The testing, fault localization and physical failure analysis of advanced package demonstrated here will provide a cost-effective method for improving manufacturing yield.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"128 1","pages":"1180-1185"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74277269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Development of compression molding process for Fan-Out wafer level packaging 扇出晶圆级封装压缩成型工艺的发展

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ECTC32862.2020.00306

Bertheau Julien, D. F.C, Kubota Tadashi, Bex Pieter, Kennes Koen, Phommahaxay Alain, Podpod Arnita, Beyne Eric, Miller Andy, Beyer Gerald

引用次数: 5

Impact of Electroless-Ni Seed Layer on Cu-Bottom-up Electroplating in High Aspect Ratio (>10) TSVs for 3D-IC Packaging Applications 用于3d集成电路封装的高宽高比(bbb10) tsv中化学- ni种子层对cu自下而上电镀的影响

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00271

M. Mariappan, M. Koyanagi, T. Fukushima

引用次数: 1

Face to Face Hybrid Wafer Bonding for Fine Pitch Applications 用于小间距应用的面对面混合晶圆键合

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00099

D. Fisher, S. Knickerbocker, Daniel Smith, R. Katz, J. Garant, J. Lubguban, V. Soler, N. Robson

引用次数: 10

Package on System Level Solder Joint Stress Analysis Under Shock Test 冲击试验下系统级焊点应力分析

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00238

Hsin-Chih Shih, HowardTW Liao, Ryan Chen, York Liao, D. Tarng, C. Hung

{"title":"Package on System Level Solder Joint Stress Analysis Under Shock Test","authors":"Hsin-Chih Shih, HowardTW Liao, Ryan Chen, York Liao, D. Tarng, C. Hung","doi":"10.1109/ectc32862.2020.00238","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00238","url":null,"abstract":"Board level drop impact tests to evaluate electronic package mounts on printed circuit board (PCB) solder joint reliability is critical, especially for handheld and mobile consumer products. Standard drop tests refer the JEDEC specification (JESD22-B111) for PCB design and testing conditions. There are several studies about the board level drop reliability of electronic products to focus on the solder joint failure mechanism (e.g., the crack location and characteristics) under the JEDEC standard. However, the literatures lack a study of the correlation of the PCB dynamic strain and solder joint stress during the board level drop impact and real product system level shock test. In this work, a 15x15 mm2 Quad Flat No Leads (QFN) package which is Wi-Fi module function used in industry scanner product was chosen to measure the peak acceleration and PCB strain under 1.2 meter height system level free drop. The maximum PCB strain would be used to correlate with standard board level drop tests to measure and calculate acceleration response. From the result, it shows that at similar PCB strain response the system level free drop tests peak acceleration is about 2900G and the board level drop tests peak acceleration is about 325G.Besides, the 3D transient numerical model based on the support excitation scheme was also performed to obtain thorough understanding of structural responses of the test vehicle and reliability of its solder joints under different test conditions. This model would be used to compute solder joint maximum interfacial normal and shear stresses. A fatigue reliability model that predicts the drop counts for different drop test conditions of JEDEC drop test condition: B (1500 G; 0.5 ms) and system-like condition: (325 G; 0.576 ms) was established. This study provides an accurate and reliable way to understand the correlation between system level and board level drop tests solder joint stress and to help to achieve service life improvements in early development stage.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"90 1","pages":"1509-1516"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78109519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study of Electromigration Failure in Solder Interconnects under Low Frequency Pulsed Direct Current Condition 低频脉冲直流条件下焊料互连电迁移失效的研究

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00119

Y. Kim, Allison T. Osmanson, Hossein Madanipou, C. Kim, P. Thompson, Qiao Chen

{"title":"Study of Electromigration Failure in Solder Interconnects under Low Frequency Pulsed Direct Current Condition","authors":"Y. Kim, Allison T. Osmanson, Hossein Madanipou, C. Kim, P. Thompson, Qiao Chen","doi":"10.1109/ectc32862.2020.00119","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00119","url":null,"abstract":"This paper concerns the electromigration (EM) failure mechanisms in solder interconnects under low frequency pulsed direct current (DC) conditions. In our study, the accelerated EM tests of Wafer-level Chip Scale Package (WCSP or WLCSP) samples are conducted under 4 different pulsed DC conditions: 0.1 Hz pulsed DC with duty factors (DFs) of 33%, 50%, 75%, and 100% (DC). The result of our testing suggests that there are at least two competing factors affecting the failure rate in an opposite manner under pulsed DC EM conditions. Specifically, when compared with the cumulative damage model (estimates the damage only during the on period), the failure kinetics is found to be more accelerated at high DF and decelerated at a lower DF. This conclusion is drawn from the observation that the EM failure rate shows an extremely nonlinear relationship with the DF and also that the failure occurs faster under a high DF than under solely DC conditions, which is not possible without a mechanism assisting the EM failure. Furthermore, it is found that there is a 2- stage resistance change before EM failure, an indication of the change in the dominant failure mechanism. The results may indicate that the pulsed DC effect on the EM failure mechanism is far more complex than anticipated with the possible involvement of a damage mechanism other than EM such as thermal fatigue.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"289 1","pages":"723-728"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76745708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Formation of smooth Au surfaces produced by multiple thin-film transfer process based on template stripping for low-temperature bonding 基于模板剥离的多层薄膜转移工艺在低温键合中的光滑金表面形成

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00047

E. Higurashi, Michitaka Yamamoto, R. Nishimura, T. Matsumae, Y. Kurashima, H. Takagi, T. Suga, T. Itoh

引用次数: 1

Direct Bonding of GaN to Diamond Substrate at Room Temperature 室温下氮化镓与金刚石衬底的直接键合

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ECTC32862.2020.00210

T. Suga, F. Mu

引用次数: 6

Irregular Bumps Design Planning for Modern Ball Grid Array Packages 现代球栅阵列封装不规则凸点设计规划

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00287

Hsin-Yu Chang, Hung-Ming Chen, Yun-Chih Kuo, Hsien-Ting Tsai, S. Chen, Jyun-Ru Jiang, Ya-Ying Chien, Yu-Yang Chen

引用次数: 2