2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"A Novel Warpage Reinforcement Architecture with RDL Interposer for Heterogeneous Integrated Packages","authors":"C. Peng, P. Lin, C. Ko, Chi-Wei Wang, Oscar Chuang, Chang-Chun Lee","doi":"10.1109/ectc32862.2020.00089","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00089","url":null,"abstract":"Over the past two decades, the multi-functions of portable electronic devices have a significant influence to change the daily life of people. To meet the requirements of short transmission path of signals, and high I/O counts, ultrathin packaging technology and novel packaging architectures are continuously progressed in accordance with the emergence of advanced technologies in global semiconductor industry. Currently, the architecture of fan out panel-level packaging (FOPLP) grows into the mainstream to meet the essentials of three-dimensional chip stacking and heterogeneous integration. Some researches suggested that the fine metal trace small than 5μm/5μm (line-width/spacing) has been carried out by using redistributed layer (RDL) first interposer technology. In the meanwhile, the package on package framework was introduced for connecting application processor and stacked memory chips, which have been gradually implemented the above-mentioned portable electronic devices. However, the warpage issue of the top and bottom packages are always a critical issue while assembled. In order to solve this issue, an additional reinforcement frame, integrated with RDL interposer is proposed to reduce its deformation caused by coefficient of thermal expansion (CTE) mismatch among the materials of packaging components. The design of reinforcement frame is 15 mm x 15 mm with a 12 mm x 12 mm cavity. There are 540 interconnections with a 300 gm of pitch at the periphery of the present package. To estimate the reliability of abovementioned novel package with efficiency, a non-linear process-oriented finite element analysis (FEA) is approached. In addition, the technique of equivalent material characteristics is also needed into FEA model to simplify the complexity of packaging structure. Finally, the better combinations to control the warpage of the present novel packaging structure through choosing the type of MUF. The warpage of packaging is obtained via the simulation methodology and provided as the designed guideline of related packaging architectures.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"70 1","pages":"526-531"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86259403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inverse Design of Substrate from Warpage Surrogate Model Using Global Optimisation Algorithms in Ultra-Thin Packages","authors":"C. Selvanayagam, Pham Luu Trung Duong, N. Raghavan","doi":"10.1109/ectc32862.2020.00360","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00360","url":null,"abstract":"The inverse design approach would be advantageous when applied to ultra-thin packages because we can design the packages for an acceptable warpage profile at the start of the design process, instead of only being able to measure the warpage after the parts are built, as is the norm with a conventional design process. A framework for the inverse design of ultra-thin electronic packages is proposed in this work. We start with the design (desired / acceptable) warpage profile and move through the framework to determine the optimum metal densities at different substrate subsections and layers that would ultimately result in the design warpage profile. The framework consists of three main phases - learning the material properties of the substrate, establishing a link between substrate design parameters and warpage and finally carrying out inverse design using a global optimization algorithm. This study utilizes a unique cocktail of machine learning techniques and algorithms to achieve this inverse design goal. Results indicate that the framework can recommend changes to the metal density distribution across the substrate in order to bring about a 20% reduction in warpage.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"2016 1","pages":"2309-2316"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86495298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D Composite Glass-silicon Interposer Integrated With Polymer Arrayed Waveguide Grating","authors":"Ziji Wang, J. Shang","doi":"10.1109/ectc32862.2020.00288","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00288","url":null,"abstract":"Integrating optical interconnects onto TSV/TGV based interposer to meet the ever-increasing chip-to-chip bandwidth demand has received continuously growing interest. Besides optical interconnections, passive optical device with relatively large footprints and low fabrication cost also holds the potential to be directly integrated onto current interposer technology. In this study, a polymer-based low-index-contrast arrayed waveguide grating(AWG) is integrated onto the 3D composite glass-silicon interposer to realize wavelength division (de)multiplexing (WDM) applications. The 3D composite interposer is fabricated by glass reflow process, polymer arrayed waveguide grating which has single mode waveguide platform is then directly fabricated onto the interposer. The feasibility of using borosilicate glass as bottom cladding of on-interposer optical waveguide and passive optical device has been verified through both simulation and experimental results. Transferring area-cost optical devices from photonics chip to composite interposer provides a promising solution to enhance the integration density.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"1844-1848"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86521457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical study of edge condensation in wafer to wafer bonding process with lattice Boltzmann approach","authors":"Jung Shin Lee, Jun Hyung Kim, Daniel Min Woo Rhee","doi":"10.1109/ectc32862.2020.00258","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00258","url":null,"abstract":"Direct wafer bonding process is applied in semiconductor production because of the advantage of attaching several chips at once. During the bonding process, the top wafer is deformed and the wafer surface is oblique from the bonding front to the edge, thereby forming a wedge-shaped flow field with a wider gap toward the edge. In this flow field, acceleration of the flow rate occurs and expansion due to pressure drop occurs. This expansion also lowers the temperature. When the temperature is sufficiently low, the vapor aggregates and the droplet condenses at the edge for wafer. Experiment on condensation reduction is difficult because of the inability to observe the flow space between wafers. It is only through numerical analysis to observe phenomena occurring in the wafer flow filed and use them to improve process recipe. In this study, numerical analysis is used to observe the condensation occurring at the edge. Numerical method enables the phase change of microscale and interface capture based on lattice Boltzmann, and added the theoretical basis for molecular behavior by adding interatomic potential including electrostatic potential of hydrogen bond. This numerical model was used to analyze the flow between wafers during bonding process and to simulate temperature drop and vapor condensation. It was observed that the vapor density decreased with time and then increased again. When the temperature is sufficiently low, the vapor aggregates and the density of the vapor increases again. A rapid rising in vapor density was observed below 2.5°C. The higher the wettability of the surface, the lower the vapor density at the cold spot. Due to the high wettability of the wafer surface, vapor is dispersed throughout the surface, and thus the amount of vapor that aggregates at the cold spot is reduced. If the wettability is higher than a certain level, a regime in which the width of the generated droplet increases with wettability appears. As a result, an optimum contact angle with minimum droplet width appears, but this may not be optimal in terms of bonding strength.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"1646-1652"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81261582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Power SOC Based on High Density MIM Capacitor for beyond Moore Era by Robust Power Integrity Achievement","authors":"Jisoo Hwang, Hoi-Jin Lee, Hyun-Yong Lee, Heeseok Lee, Minkyu Kim, Youngmin Shin","doi":"10.1109/ectc32862.2020.00343","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00343","url":null,"abstract":"In this paper, the methods for improving the PI (Power Integrity) of low power SOC (System-On-Chip) are discussed. In order to confirm the PI improvement effect by using MIM (Metal-Insulator-Metal), system-level PDN impedance and voltage drop was analyzed for cores with one LICC (Low Inductance Ceramic Capacitor) embedded in the package. Compared to the case where no decoupling capacitor was applied, the PI characteristics were improved when the LICC (Low Inductance Ceramic Capacitor) was inserted in the package substrate, and more dramatic improvement can be achieved by using MIM. When the embedded decoupling capacitor and the MIM capacitor corresponding to the core area are used at the same time, the system-level PDN impedance is reduced by less than half compared with the case where only the embedded LICC is used. Also, it was confirmed by simulation and measurement that voltage drop and voltage ripple can be reduced by implementing MIM. In particular, MIM has been analyzed to be more effective at high frequencies than conventional ceramic capacitors, making it a suitable PI improvement solution for the beyond Moore era.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2203-2208"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85115340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Processing Glass Substrate for Advanced Packaging using Laser Induced Deep Etching","authors":"R. Santos, J. Delrue, N. Ambrosius, Roman Ostholt, S. Schmidt","doi":"10.1109/ectc32862.2020.00300","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00300","url":null,"abstract":"This work presents a new concept for using glass as a component material in FOWLP. Glass exhibits excellent properties for advanced packaging applications, such as low loss tangent, low dielectric constant, CTE values between that of Si and a typical EMC, and a favorable Young’s modulus for reducing warpage. Despite the great interest in the properties of glass, its use is still not widespread as traditional glass processing techniques have a detrimental impact on its properties while increasing the effective material cost. Here, we show that by using Laser Induced Deep Etching technology for processing glass, substrates can be produced in an economical manner while retaining all of the its excellent properties. Furthermore, this technology enables the processing of precise cavities with flexible features completely made of glass, capable of passively correcting die position errors occurring during the pick-and-place and EMC-related processes. In addition, issues such as warpage are highly reduced while allowing the integration of other features such as Through Glass Vias and Integrated Passive Devices in the same wafer.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"1922-1927"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90491294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chemical thinning approach for high-topography glass wafers","authors":"M. Bedjaoui, J. Brun, Steve W. Martin, R. Salot","doi":"10.1109/ECTC32862.2020.00021","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00021","url":null,"abstract":"In this paper, a novel processing scheme for the thinning of high-topography glass wafers and its use for the fabrication of thin film battery devices is reported. The approach involves different engineering steps from the fabrication of battery stacks on 8\" rigid alkali-free glass wafers (initial thickness of 500μm) to the delivery of individual battery devices on etched glass (final thickness from 100pm to 50μm). In particular, we introduce the chemical etching solutions, the used masking materials as well as the technique of battery wafers mounting. This scheme, therefore, allows a wet etching of the rear surface of battery wafers in such a way that the etching system does not disturb the electrochemical properties of thin film batteries. Using the proposed method, fully functional thin film batteries (thickness of 40μm, size of 7mmx7mm) on ultrathin glass (50μm±5μm) were achieved.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"49-55"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89203123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extracting power supply current profile by using interposer-based low-noise probing technique for PDN design of high-density POP","authors":"Heeseok Lee, Hoi-Jin Lee, Jisoo Hwang, Taekeun An, Seok-Ha Hong, Youngmin Shin","doi":"10.1109/ECTC32862.2020.00276","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00276","url":null,"abstract":"Firmly understanding the power supply current profile (PSCP) of various scenarios used in real use cases is essential for the simulation and design of power delivery network (PDN) of system-on-chip (SOC) to maximize processor’s performance within limited cost budget for die, package, and system, because the low power hard-ware implementation of leading-edge SOC including high performance computing cores for video data processing, 3D graphics, augmented reality, artificial intelligence, and 5G data communication with battery powered portable electronic devices, whose primary concern is the low power consumption, has been concentrated on reducing the minimum allowable power supply voltage for high performance computing cores including CPU, GPU, NPU and CP. The objective of this work is presenting the method to precisely probe power supply voltage fluctuation (PSVF) of whole power domains for power supply current profile (PSCP) extraction of entire cores, for which the authors present an concrete analysis methodology, based on which a test interposer scheme targeted for probing core logic blocks at the proper position of PDN is implemented and demonstrated when in operation. The proposed low noise probing system for acquiring PSCP is constructed by a test interposer designed with rigorous PI analyses.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"1769-1774"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84330905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design, Process and Reliability of Face-up 2-layer molded FOWLP Antenna-in-Package","authors":"C. T. Chong, Lim Teck Guan, Han Yong, F. Che, David Ho Soon Wee, S. Chong","doi":"10.1109/ectc32862.2020.00016","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00016","url":null,"abstract":"Fan-Out WLP with 2-layer molded structure have been proposed for high performance Antenna-in-Package (AiP) for 5G mmWave applications with improved thermal dissipation capability. MMIC chip is embedded in lower mold compound layer with chip facing up to enable the backside of chip to be designed with direct connection to thermal solution to PCB. The feedlines are implemented in-between top and bottom Epoxy Molding Compound (EMC) layers and there can be enhanced with ground layer for minimizing interference from antenna to RF feedline and MMIC. The electrical, mechanical and thermal design considerations, process integration and package reliability are described.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88467682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Warpage Liquid Compression Molding (LCM) Material for High Density Fan-out and Wafer Level Packaging Applications","authors":"Jay Chao, Rong Zhang, T. Do, AnhBinh Tong, Yijia Ma, David Grimes, R. Trichur, Lirong Bao","doi":"10.1109/ectc32862.2020.00151","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00151","url":null,"abstract":"Wafer level encapsulation is an important packaging process for several components in mobile and high-performance computing applications. In mobile applications, electronic components like application processors, radio-frequency System in Package (RF-SiP) and antenna modules are being manufactured using wafer level fan-out processes. In HPC, wafer level encapsulation is used for chip-on-wafer (CoW) processing and 2.5D / 3D packaging that enables wafer level packaging of processors and high band width memory devices. Although encapsulant materials are currently used in mass production, many pain points remain unresolved. These are predominantly related to lowering the wafer level warpage to enable better handling of wafers during processing, addressing the environmental and EU REACH regulatory compliance, providing better total cost of ownership to the end user by improving throughput and various other factors. In our development, we aim to address these pains and we will present our progress in this research paper. As the structural material in the package, molding compound can cause severe warpage issue during process, becoming the limiting factor to pursue thinner packaging design and causing serious wafer handling issues in the equipment during wafer processing. However, we considered a new material design route to develop ultra-low warpage LCM materials that can dramatically reduce the warpage thereby benefitting various WLP packaging design, such as Fan-in or Fan-out type. We have successfully demonstrated more than 70% improvement in warpage compared to traditional LCM compound. This new type of LCM material is REACH compliant and shows good warpage stability after high temperature annealing process. The polymer relaxation study shows the unique relaxation behavior leading to the warpage stability that is critical in many Fan-out processes. Dynamic Mechanical Analysis is the useful tool to study the relaxation behavior that can differentiate the impact of various chemistry on epoxy molding materials. Another key advantage of our LCM is the excellent gapfilling capability that can lead to the protection of high density structures in semiconductor packages with finer die-to-die or die-to-substrate spacing, meanwhile enabling low-warpage and simpler processing steps. Moreover, the new LCM design can help further shorten the molding time, allowing for increased throughput resulting in lower cost of ownership for the end users.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"924-930"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88078382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}