2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Investigation on the Mechanical Behavior Evolution Occurring in Lead Free Solder Joints Exposed to Thermal Cycling","authors":"Abdullah Fahim, S. K. Kamrul Hasan, J. Suhling, P. Lall","doi":"10.1109/ectc32862.2020.00235","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00235","url":null,"abstract":"In electronic packages, solder joints are frequently exposed to thermal cycling environment where temperature variations occur from very low to high temperature. These exposures can occur in real life applications as well as in accelerated thermal cycling tests used for the characterization of thermal-mechanical fatigue behavior. Due to temperature variations and CTE mismatches of the assembly materials, cyclic temperature leads to damage accumulation due to shear fatigue and material property evolves in the solder joints. In addition, the thermal cycling dwell periods at the high temperature extremes will cause thermal aging phenomena in the solder material. This leads to microstructural evolution and material property degradation. Further aging effects can occur during the ramp periods between the low and high temperature extremes of the cycling.While changes in solder materials during aging have been examined in detail in prior studies, there have been limited studies examining material evolution occurring during thermal cycling. In a previous study of the authors, mechanical behavior evolutions of SAC305 lead-free solder material under several different thermal cycling profiles have been reported. The results demonstrated severe degradations in the mechanical properties, especially for thermal cycles with the long ramp and dwell periods. In our other recent work, evolution of the mechanical behavior of real solder joints has been investigated. In the current investigation, these prior studies have been extended. In particular, the mechanical behavior evolutions in both bulk SAC305 solder samples and SAC305 solder joints have been investigated under the same slow thermal cycling profile, and then the results were compared.In the first part of this study, miniature bulk solder uniaxial test specimens were prepared by reflowing solder in rectangular cross-section glass tubes with a controlled temperature profile. After reflow solidification, the samples were placed into the environmental chamber and thermally cycled between -40 C to +125 oC under a stress-free condition (no load). The thermal cycle consisted of 150 minutes cycles with 45 minutes ramps and 30 minutes dwells. The test specimens were separated into groups that were subjected to various durations of cycling (e.g. 0, 10, 50, 100, 250 cycles, etc.). After the environmental exposures, stress-strain curves of the cycled uniaxial samples were recorded, and then the mechanical properties were measured including the effective elastic modulus (E), yield stress (YS), ultimate tensile strength (UTS). The evolutions of the mechanical properties were characterized as a function of number of applied thermal cycles.In the second part of this study, the evolution of the mechanical behavior in thermally cycled BGA solder joints was studied using nanoindentation. PBGA solder joint strip specimens were first prepared by cross sectioning BGA assemblies followed by surface polishing to facilitate nanoi","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"1486-1495"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74071353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polyimide Fine-via Etching and Low-damage Surface-modification Process For High-density Fan-out Wafer Level Package","authors":"Y. Morikawa, Daisuke Hironiwa, T. Murayama","doi":"10.1109/ectc32862.2020.00147","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00147","url":null,"abstract":"In the last years the number of high performance mobile devices, such as smart phones or tablet PCs, increases widely and accordingly data traffic augments rapidly. Devices for these equipment require high-rate processing capabilities, high-density packaging possibilities and low power consumptions for data-center and servers. Thus the demand for packed semiconductor chips with high density of components is growing. In order to accomplish high-density packaging, miniaturization technology of wiring in heterogeneous Fan-out Wafer Level Packaging (FO-WLP) is needful to multi chip module system fabrication using by the re-distribution layer (RDL) wiring technologies. To obtain the fine vias and line/space in a polyimide film, the PVD sputtering and electro-Cu deposition processes are widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line / space in the FO-WLP process. The second is that PVD sputtering process for high adhesion between Cu and polyimide films is also will be issue by status of surface and surface residue. The third is that surface damage of polyimide by the plasma irradiation (Ions, UV), moisture absorption.In this paper, we report the role of the dry etching to fabricate the RDL. The dry etching has already applied in various RDL fabrication process, such as dry descum process, the surface modification process and so on. Dry descum process is named that the process is the removal of photoresist (PR) residues after photo-lithography. The surface modification process has two major functions. First is the improvement of the interface adhesion of the films. To improve of the adhesion, it is necessary that the change of surface morphology. As one way, the changing of the surface configuration is suggested. To obtain the surface with large roughness, the etching process is recommended that the bombardment characteristics is more effective. As the result, the contact area is increased by the etching, so the adhesion would be improved. Alternatively, the application of the chemical response between films is suggested. To generate the chemical function groups, the etching process is recommended that the chemical response is more effective. These surface morphology is adjusted by dry etching condition. In this study, we focus the control of hydrophilic property using dry etching process. In RDL process, it is important to conduct a pre-treatment of electro-Cu deposition processes. When the polymer surface has hydrophobic characteristic, Cu plating solution would be rejected from the surface of polymer. Then, the plating solution cannot enter the bottom position of channels in polymer films, and the voids may be generated. In the future, these channels would be become reduced in size, therefore the control of hydrophilic property would be focused.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"900-905"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74826807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of Embedded Glass Wafer Fan-Out Package With 2D Antenna Arrays for 77GHz Millimeter-wave Chip","authors":"Tian Yu, Xiaodong Zhang, Li Chen, Xiaoli Ren, Zongming Duan, Daquan Yu","doi":"10.1109/ectc32862.2020.00018","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00018","url":null,"abstract":"Fan-out wafer level package (FO-WLP) technology provides an ideal approach for millimeter-wave (mm-Wave) chip with higher I/O density, excellent electrical performance and greater design flexibilities. In this paper, a package with the size of 9.46mm×9.77mm for 77GHz automotive radar chip with size of 5.89mm×5.83mm is developed by embedded glass fan out (eGFO) technology. And then a high electrical performance solution for antenna-in-package (AiP) is demonstrated. A number of antennas are designed and fabricated on the top of the package using redistribution layer (RDL). The eGFO package with antennas has a size of 23.1mm×10.7mm with 220μm thin body thickness and a footprint with a standard ball pitch of 0.5mm. There are antenna arrays for receiver and transmitter which are distributed on the same plane of the chip surface and located on two sides of the chip. The ground plane on the top of the printed circuit board (PCB) is used as a reflector for the integrated antenna. Simulation results show that present eGFO can provide a high electrical performance solution for automotive radar packaging with AiP.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"121 1","pages":"31-36"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78431178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Handling Solution for Easy Processing of Thin Glass with TGV","authors":"S. Nelson, D. Levy, A. Shorey","doi":"10.1109/ectc32862.2020.00309","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00309","url":null,"abstract":"Glass substrates with through-glass vias for electronic packaging and radio-frequency substrate applications have been demonstrated in a variety of formats from wafers to panels, yet adoption has been hindered by difficulty in handling thin glass in the fab. In this paper we describe successful processing of glass wafers on silicon handles, using our polymer-free temporary bonding process. One preferred handle is silicon, so that the glass- on-silicon unit is rigid, opaque, and compatible with existing silicon-processing equipment. With the Mosaic bond approach, no adhesive wicks into the glass vias, allowing good via fill. Furthermore, no solvent is required for post-debond cleaning. In this paper, we demonstrate fundamental process capability for implementation of this technology for volume manufacture of glass solutions.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"39 1","pages":"1986-1991"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75082526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A design and fabrication of transmission line for eSiFO in millimeter-wave applications","authors":"Shengjuan Zhou, Jian Cai, Qian Wang, Xiuyu Shi, Xuesong Zhang, Changmin Song, Yu Chen","doi":"10.1109/ectc32862.2020.00342","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00342","url":null,"abstract":"In millimeter-wave devices, Fan-out Wafer Level Package for system integration is a popular trend to meet the requirements of high performance, small dimensions and low cost. Compared to conventional Fan-out Wafer Level Package with molding compound, embedded Silicon Fan-out (eSiFO) Wafer Level Package has become an attractive technology due to low cost, less warpage problem and fine-pitch redistribution layer (RDL) production capability. However, silicon substrate is usually of low resistivity, which limits the application of eSiFO technology in millimeter-wave field. Thus, high efficiency and low loss transmission line has become an important topic in eSiFO. In this paper, a design of coplanar waveguide (CPW) with shield line for eSiFO in millimeter-wave applications is proposed. Electrical modeling of transmission line structure was carried out by HFSS. The CPW with and without shield line were fabricated compatible with semiconductor processes. Measurement and test results shows the shield line can provide good impedance matching, suppress undesirable substrate loss, as well as decrease crosstalk from adjacent lines.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"270 1","pages":"2197-2202"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77819134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Wireless Battery-less Seat Sensor for Autonomous Vehicles","authors":"Saikat Mondal, Kanishka P. Wijewardena, Saranraj Karrapuswami, Deepak Kumar, P. Chahal, M. Ghannam, Mark A. Cuddihy","doi":"10.1109/ECTC32862.2020.00357","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00357","url":null,"abstract":"In this paper, a miniaturized battery-less passive transponder for wireless seat sensing is designed and demon-strated. As automobiles become smarter, more sensors are required to monitor multiple parameters within and outside the vehicle. Naturally with a greater number of sensors, the amount of wire harnesses required to transfer data and power supply will increase thus leading to increase in weight and cost of vehicle. Battery-free wireless sensors are an excellent alternative to wired sensors to meet this challenge. In addition, battery-less senors offer easier service and design or packaging flexibility. In this paper, a system which powers and reads magnetic switch sensor for seat belt status detection is demonstrated based on a wireless battery-less RFID platform.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"356 1","pages":"2289-2294"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80134943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedded Power Inductor in Organic Substrate with Novel Magnetic Epoxy","authors":"Chi-Hao Chiang, Thomas Wang, Shu-Ting Yang, Pao-Nan Lee, Wei-Yu Nien, CT Lee, Sidney Huang, Harrison Chang","doi":"10.1109/ectc32862.2020.00246","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00246","url":null,"abstract":"The high power computing for AI and Data Centers are advancing rapidly and power efficiency becomes critical. Ways of power integration are being explored, with inductor being one of the most challenging topics. Embedding inductor in organic substrate with magnetic material is a popular approach, for the benefit of lower cost, good scalability, and future integrating roadmap. Modeling of power inductors is studied, and comparison between measurement and simulation are used to validate the modeling and verify predictions. By studying various conductor geometry and magnetic material location, an optimized inductor design approach is shown. Novel magnetic epoxy material is chosen with lamination process introduced. It is found that embedded power inductor with high inductance per area can be implemented the methods described in this paper, and a co-design approach can be used to design the power electronics using the embedded inductor with magnetic material. [1]","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"1566-1572"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81541318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2-tier Embedded 3D Capacitor with High Aspect Ratio TSV","authors":"K. Chui, I-Ting Wang, Faxing Che, Zhixian Chen, Xiangy-Yu Wang, W. Loh, Qin Ren, L. Ji, Yao Zhu","doi":"10.1109/ectc32862.2020.00101","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00101","url":null,"abstract":"This paper describes the concept and demonstration of a 2-tier MIMIM capacitor that can be placed around a TSV. By fabricating the metal-insulator-metal-insulator-metal (MIMIM) capacitor around the TSV, more than 30× increase in capacitance over a planar capacitor occupying the same planar area can be achieved. High-k dielectric, HfO2 is deposited using Atomic Layer Deposition (ALD) process for good and uniform coverage required in TSV. By employing an insulator with large dielectric constant (with reference to SiO2), capacitance can be increased significantly. Thermomechanical simulations have verified that there is little impact to the stress induced in the Si and Keep-Out-Zone (KOZ) of TSVs around which the MIMIM capacitor is embedded.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"611-616"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81846846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Laser-assisted bonding (LAB) and de-bonding (LAdB) as an advanced process solution for selective repair of 3D and multi-die chip packages","authors":"Matthias Fettke, Timo Kubsch, Andrej Kolbasow, Vinith Bejugam, Alexander Frick, T. Teutsch","doi":"10.1109/ectc32862.2020.00165","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00165","url":null,"abstract":"This paper describes an advanced method for repairing assembled 3D and multi-die chip packages using a unique process involving laser assisted bonding (LAB) and laser assisted de-bonding (LAdB); i.e. \"Laplace\". Using a laser as medium for inducing the thermal load into a soldered interface of a chip-assembly generates many technical advancements with reference to processing, thermal and mechanical stresses and life-time. This paper reveals the basic mechanism and process flow of LAdB involving the characterization of different phases during de-bonding, along with the results of a feasibility study. For the feasibility study, 4 different test substrates were used, a 3D chip-on-chip package, a chip-on-wafer, and 2 different chip-on-board configurations. The impact of sequential single die removal using LAdB, and accompanying chip replacement using LAB were analysed. The underlying test materials used were Si-chips, with 40μm Sn-plated Cu-pillars, and Si-chips placed with 200μm SAC305 (Sn 96.5%, Au 3.0%, Cu 0.5%) solder bumps over 5μm pads subjected to 5μm electroless nickel immersion gold (ENIG). The chips were stacked resulting in up to 6 layers.The main question, whether the use of a given number of laser-assisted repair cycles before a solder bond interface would weaken is explored in the current work using a 130μm SAC305 solder bump interface. The interface was formed between the plated pads of Si-chip and a printed circuit board (PCB) board with CuNiAu finish.Analysis of thermal load/thermal distribution in the package during the removal and placement sequence were measured using a contactless/non-invasive thermooptical sensor element. The ensuing impact on the metallurgical properties and acicularintermetallic compound (IMC) layers corresponding to adjacent interfaces after multiple de-bonding and re-bonding steps were analysed by cross-sectional analysis, scanning electron microsope (SEM), energy-dispersive x-ray spectroscopy (EDX) and optical microscopy. The mechanical stress was identified by an optical surface flatness measurement tool before and after the chip re-placement steps.Tests related to thermal cycling, metallurgical analysis and mechanical shear were conducted to finally generate the number of possible chip replacements using LAB and LAdB processes before the soldered interfaces reached a critical limit of stability and reliability. In conclusion potential applications and future prospects of intended reliability and stability are outlined.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"351 1","pages":"1016-1024"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84871763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Very low parasitic inductance double side cooling power modules based on ceramic substrates and GaN devices","authors":"Christine Laurant, J. Delaine, P. Perichon, B. Thollin, Charley Lanneluc, Antoine Izoulet, Manon Porlan, R. Escoffier, J. Brun, J. Favre","doi":"10.1109/ectc32862.2020.00222","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00222","url":null,"abstract":"In this work, a new 650V double-side cooling inverter leg, using ceramic substrates and bare GaN on silicon transistors, compatible with high operating temperature, has been designed, manufactured and tested. It exhibits a parasitic inductance of 3 nH at 100 MHz. This paper firstly presents a review of parasitic elements reduction in power modules, and then it describes in details the technology, the design optimization, the original test strategy, the manufacturing process, and finally presents and discuss the electrical results.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"99 1","pages":"1402-1407"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85488932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}