2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Low Power SOC Based on High Density MIM Capacitor for beyond Moore Era by Robust Power Integrity Achievement","authors":"Jisoo Hwang, Hoi-Jin Lee, Hyun-Yong Lee, Heeseok Lee, Minkyu Kim, Youngmin Shin","doi":"10.1109/ectc32862.2020.00343","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00343","url":null,"abstract":"In this paper, the methods for improving the PI (Power Integrity) of low power SOC (System-On-Chip) are discussed. In order to confirm the PI improvement effect by using MIM (Metal-Insulator-Metal), system-level PDN impedance and voltage drop was analyzed for cores with one LICC (Low Inductance Ceramic Capacitor) embedded in the package. Compared to the case where no decoupling capacitor was applied, the PI characteristics were improved when the LICC (Low Inductance Ceramic Capacitor) was inserted in the package substrate, and more dramatic improvement can be achieved by using MIM. When the embedded decoupling capacitor and the MIM capacitor corresponding to the core area are used at the same time, the system-level PDN impedance is reduced by less than half compared with the case where only the embedded LICC is used. Also, it was confirmed by simulation and measurement that voltage drop and voltage ripple can be reduced by implementing MIM. In particular, MIM has been analyzed to be more effective at high frequencies than conventional ceramic capacitors, making it a suitable PI improvement solution for the beyond Moore era.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2203-2208"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85115340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inverse Design of Substrate from Warpage Surrogate Model Using Global Optimisation Algorithms in Ultra-Thin Packages","authors":"C. Selvanayagam, Pham Luu Trung Duong, N. Raghavan","doi":"10.1109/ectc32862.2020.00360","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00360","url":null,"abstract":"The inverse design approach would be advantageous when applied to ultra-thin packages because we can design the packages for an acceptable warpage profile at the start of the design process, instead of only being able to measure the warpage after the parts are built, as is the norm with a conventional design process. A framework for the inverse design of ultra-thin electronic packages is proposed in this work. We start with the design (desired / acceptable) warpage profile and move through the framework to determine the optimum metal densities at different substrate subsections and layers that would ultimately result in the design warpage profile. The framework consists of three main phases - learning the material properties of the substrate, establishing a link between substrate design parameters and warpage and finally carrying out inverse design using a global optimization algorithm. This study utilizes a unique cocktail of machine learning techniques and algorithms to achieve this inverse design goal. Results indicate that the framework can recommend changes to the metal density distribution across the substrate in order to bring about a 20% reduction in warpage.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"2016 1","pages":"2309-2316"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86495298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Imprint-Through Mold Via (i-TMV) with High Aspect Ratio and Narrow Pitch for Antenna in Package","authors":"Xinrong Li, T. Ogawa, T. Shibata, S. Yoneda, N. Suzuki, T. Nonaka","doi":"10.1109/ECTC32862.2020.00032","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00032","url":null,"abstract":"The imprint-Through Mold Via was proposed for electromagnetic interference (EMI) shielding of Antenna in Package (AiP) application. The 300 μm-height via array could be successfully imprinted by using the silicon master which has 743 pillars with the diameter of 100 μm, pitch of 200 μm and height of 370 μm, and the via array was well filled by vacuum printing method with newly developed conductive paste utilizing transient liquid phase sintering. In order to evaluate the electric characteristics of the via array, a daisy-chain test vehicle (TV) which could connect all the vias together was fabricated. In the result of the reliability test, no electrical failure was confirmed of this daisy-chain.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"119 1","pages":"120-125"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86104233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Warpage Reinforcement Architecture with RDL Interposer for Heterogeneous Integrated Packages","authors":"C. Peng, P. Lin, C. Ko, Chi-Wei Wang, Oscar Chuang, Chang-Chun Lee","doi":"10.1109/ectc32862.2020.00089","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00089","url":null,"abstract":"Over the past two decades, the multi-functions of portable electronic devices have a significant influence to change the daily life of people. To meet the requirements of short transmission path of signals, and high I/O counts, ultrathin packaging technology and novel packaging architectures are continuously progressed in accordance with the emergence of advanced technologies in global semiconductor industry. Currently, the architecture of fan out panel-level packaging (FOPLP) grows into the mainstream to meet the essentials of three-dimensional chip stacking and heterogeneous integration. Some researches suggested that the fine metal trace small than 5μm/5μm (line-width/spacing) has been carried out by using redistributed layer (RDL) first interposer technology. In the meanwhile, the package on package framework was introduced for connecting application processor and stacked memory chips, which have been gradually implemented the above-mentioned portable electronic devices. However, the warpage issue of the top and bottom packages are always a critical issue while assembled. In order to solve this issue, an additional reinforcement frame, integrated with RDL interposer is proposed to reduce its deformation caused by coefficient of thermal expansion (CTE) mismatch among the materials of packaging components. The design of reinforcement frame is 15 mm x 15 mm with a 12 mm x 12 mm cavity. There are 540 interconnections with a 300 gm of pitch at the periphery of the present package. To estimate the reliability of abovementioned novel package with efficiency, a non-linear process-oriented finite element analysis (FEA) is approached. In addition, the technique of equivalent material characteristics is also needed into FEA model to simplify the complexity of packaging structure. Finally, the better combinations to control the warpage of the present novel packaging structure through choosing the type of MUF. The warpage of packaging is obtained via the simulation methodology and provided as the designed guideline of related packaging architectures.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"70 1","pages":"526-531"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86259403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid package for high performance Inertial Measurement Units","authors":"M. Del, A. Gritti, Douglas Lodgson, D. Cheng, N. Manca, R. Duca, T. Lao, Yiyi Ma","doi":"10.1109/ectc32862.2020.00075","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00075","url":null,"abstract":"In the field of MEMS sensors, package plays a primary role since it strongly affects device behavior and performance. Depending on the application and mission profile, design and package technology need to be targeted in order to fit the best the given requirements.When sensors work in harsh environments like in automotive applications, system is subject to very aggressive thermal cycles. Neglecting cost aspects, main and conflicting features are electrical performance stability and package board level reliability.Due to the high mechanical stiffness and due to the coefficient of thermal expansion matched versus that of silicon, ceramic cavity packages limit the stress transfer to the MEMS sensor ensuring high performance in terms of stability. However, the substantial mechanical proprieties discrepancy compared to that of PCB, implies stress absorption at solder joint level causing reduced board level reliability performance. Cavity packages based on organic substrate, show opposite behavior. If on the one hand they shift the stress concentration toward the substrate increasing board level reliability, on the other they worsen package-to-MEMS decoupling and thus the stability performance.In this paper a hybrid package is presented to achieve optimal trade-off between stability and reliability requirements. Proposed solution is based on a Si-interposer glue-bonded on the substrate, ASIC and MEMS dice are attached on top of it. Si-interposer provides stiff substrate with low coefficient of thermal expansion ensuring package-to-MEMS decoupling. Organic substrate shifts stress concentration to the interposer DA material increasing board level reliability performance.Numerical analysis has been performed to properly design the package. Focus is given to solder joint reliability at the thermal cycles. Experimental solder joint reliability test and electrical performance characterization are finally presented to confirm the effectiveness of the proposed approach.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"425-431"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78463819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extracting power supply current profile by using interposer-based low-noise probing technique for PDN design of high-density POP","authors":"Heeseok Lee, Hoi-Jin Lee, Jisoo Hwang, Taekeun An, Seok-Ha Hong, Youngmin Shin","doi":"10.1109/ECTC32862.2020.00276","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00276","url":null,"abstract":"Firmly understanding the power supply current profile (PSCP) of various scenarios used in real use cases is essential for the simulation and design of power delivery network (PDN) of system-on-chip (SOC) to maximize processor’s performance within limited cost budget for die, package, and system, because the low power hard-ware implementation of leading-edge SOC including high performance computing cores for video data processing, 3D graphics, augmented reality, artificial intelligence, and 5G data communication with battery powered portable electronic devices, whose primary concern is the low power consumption, has been concentrated on reducing the minimum allowable power supply voltage for high performance computing cores including CPU, GPU, NPU and CP. The objective of this work is presenting the method to precisely probe power supply voltage fluctuation (PSVF) of whole power domains for power supply current profile (PSCP) extraction of entire cores, for which the authors present an concrete analysis methodology, based on which a test interposer scheme targeted for probing core logic blocks at the proper position of PDN is implemented and demonstrated when in operation. The proposed low noise probing system for acquiring PSCP is constructed by a test interposer designed with rigorous PI analyses.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"1769-1774"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84330905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strategies relating to CMP for die to wafer interconnects utilizing hybrid direct bonding","authors":"J. S. Sierra Suarez, John P. Mudrick, Crystal C. Sennett, T. Friedmann, Shawn Arterburn, M. Jordan, L. Caravello, J. Gutierrez, M. David Henry","doi":"10.1109/ectc32862.2020.00304","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00304","url":null,"abstract":"In this study we examine a split-foundry multilevel application specific integrated circuit (ASIC) Si-interposer and die bonded using the direct bond interface (DBI) process, in addition to shortloop vehicles. The designs have been subject to relaxed pattern density rules, and exhibit chemical mechanical planarization (CMP) systematic process issues of varying degrees. We find that the interconnect formation is robust against moderate dielectric thickness variation, as well as a moderate degree of copper corrosion. We discuss and demonstrate various CMP methods which have a clear and repeatable impact. Pattern density effects and defectivity on the bond quality are examined using focused ion beam scanning electron microscope (FIB-SEM) images at the feature scale (sub 100 um) and intra-die scale (few mm). Impact to the CMP performance, including plug recess, and defectivity are discussed.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1950-1956"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83948450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Processing Glass Substrate for Advanced Packaging using Laser Induced Deep Etching","authors":"R. Santos, J. Delrue, N. Ambrosius, Roman Ostholt, S. Schmidt","doi":"10.1109/ectc32862.2020.00300","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00300","url":null,"abstract":"This work presents a new concept for using glass as a component material in FOWLP. Glass exhibits excellent properties for advanced packaging applications, such as low loss tangent, low dielectric constant, CTE values between that of Si and a typical EMC, and a favorable Young’s modulus for reducing warpage. Despite the great interest in the properties of glass, its use is still not widespread as traditional glass processing techniques have a detrimental impact on its properties while increasing the effective material cost. Here, we show that by using Laser Induced Deep Etching technology for processing glass, substrates can be produced in an economical manner while retaining all of the its excellent properties. Furthermore, this technology enables the processing of precise cavities with flexible features completely made of glass, capable of passively correcting die position errors occurring during the pick-and-place and EMC-related processes. In addition, issues such as warpage are highly reduced while allowing the integration of other features such as Through Glass Vias and Integrated Passive Devices in the same wafer.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"1922-1927"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90491294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromechanical finite element analysis for designed low-frequency MEMS piezoelectric vibration energy harvester","authors":"Ling Xu, Shengrui Zhou, Ying Xiang, Yinglin Yang","doi":"10.1109/ectc32862.2020.00327","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00327","url":null,"abstract":"This work presents an electromechanical finite element analysis for a proposed MEMS piezoelectric vibration energy harvester. The structure of the MEMS energy harvester consists of a basic cantilever beam with a clamped end mass and a spring net which can enhance the reliability of the device. Aluminum nitride thin film is applied as the piezoelectric function material. The proposed MEMS device is also fabricated, packaged and characterized to determine its performance. The spring net structure design is proven to increase the yield of the MEMS energy harvester chips during transportation. Three dimensional electromechanical finite element model coupled the solid mechanics physics and electrostatics physics is built to simulate the piezoelectric effect. The simulated results and the experimental measured data are in close agreement, which verified the prediction of the finite element model. The validation of the model indicate that the finite model can instruct the design of an ideal MEMS piezoelectric device in short period at a low cost.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"2112-2117"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90354787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine-Pitch Interconnection and Highly Integrated Assembly Packaging with FOMIP (Fan-out Mediatek Innovation Package) Technology","authors":"I. Hsu, Chi-Yuan Chen, Stanley Lin, Ta-Jen Yu, M. Hsieh, K. Kang, S. Yoon","doi":"10.1109/ectc32862.2020.00142","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00142","url":null,"abstract":"The market for mobile data access devices connected to a virtual cloud access point is exploding and driving both increased functional convergence as well as increased packaging complexity and sophistication. This is driving an unprecedented demand to increase the variety of advanced packages, such as chiplets and TSV (Through Silicon Via) interposer packaging solutions. It is expected that the industry will see more exciting interconnect technologies of advanced wafer level packaging such as TSV, 2.5D interposers, TSV-less (die last), eWLB (embedded Wafer Level Ball Grid Array)/FOWLP (Fan Out Wafer Level Package) to meet these needs. Because demands of die size reduction, efficiency enhancement and lower power consumption are always required in mobile communication applications with advanced Si node, much finer line width/space (LW/LS) and die pad pitch design is utilized. However, when the finer LW/LS design is used in the advanced Si node electronic devices, not only will there be an increased cost, but also the substrate manufacturing capability in a flip chip package must be considered. The substrate technology with finer LW/LS of 5/5μm and below currently is still a tough challenge in manufacturing. Therefore, in order to deliver a cost-efficient, fine pitch interconnection, highly integrated and performance packaging solution, the FOMIP (Fan-out Mediatek Innovation Package) technology is introduced in this paper. The FOMIP technology adopts 2.5D eWLB and flip chip package technologies with the design of 60μm die pad pitch, 5/5μm LW/LS and 1 layer redistribution layer (RDL) to extend the interconnection pitch as minimum 80μm by Cu pillar bumping process. The assembly challenges and process development including how to optimize the equipment handling and the warpage characterization of molded wafer is present. The warpage of molded wafer with Cu pillar bumps is collected to analyze different processes before eWLB package singulation. The molded eWLB package is adopted as a flip chip die to attach on a 2-layers embedded trace substrate (ETS) with LW/LS of 10/10μm by using cost-effective mass reflow (MR) chip attach process. To examine the quality and yield of the structure, package level long-term reliability tests are performed. Based on these results, it is believed that this examined FOMIP technology can be a robust, low profile and cost-effective package solution when much finer LW/LS and pitches in the die level design are utilized, such as 40μm die pad pitch with 2/2μm LW/LS and 1 layer RDL design and below.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"99 1","pages":"867-872"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79266263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}