2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Identification of polymer materials in electronic packages including counterfeit prevention","authors":"Junbo Yang, Jiefeng Xu, Seungbae Park","doi":"10.1109/ectc32862.2020.00361","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00361","url":null,"abstract":"Epoxy-based underfill materials are widely used in microelectronic packaging to reduce coefficient of thermal expansion (CTE) mismatch between the organic substrate and the silicon chip and thermal stresses on the solder joints. The lack of information about the underfill material type together with its material properties can be a real hindrance to researchers when they deal with simulations involved with various underfills. Therefore, getting the correct material properties of underfill materials can enhance the reliability of simulation results to achieve the optimal solution, which significantly reduces experiment costs and time. A novel identification method for cured underfill materials from assembled packages is presented in this paper. Because the underfill materials are tiny size, insoluble in organic solvent and hard to harvest issues, the Fourier-transform infrared spectroscopy microscope Attenuated total reflectance (FT-IR Microscope ATR) have been proposed as a proper method to detect the underfill materials from assembled package. The fingerprint region of each material spectrum is chosen to apply the chemometrics to build the discriminant models. The soft independent modeling of class analogy (SIMCA) method is used to create a classification model that exhibits a high discrimination power ratio. By increasing the number of training sets and the confidence limit, the SIMCA model showed almost 100% accuracy on identification of UF1230, EP1641, SMT88U, and SMC-375TGSF5, which indicates its superior ability to discriminate underfill material with low risk of misclassification. In this study, the method of collecting dispensed or cured underfill material data from assembled packages is also presented.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2317-2324"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91123866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Package on System Level Solder Joint Stress Analysis Under Shock Test","authors":"Hsin-Chih Shih, HowardTW Liao, Ryan Chen, York Liao, D. Tarng, C. Hung","doi":"10.1109/ectc32862.2020.00238","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00238","url":null,"abstract":"Board level drop impact tests to evaluate electronic package mounts on printed circuit board (PCB) solder joint reliability is critical, especially for handheld and mobile consumer products. Standard drop tests refer the JEDEC specification (JESD22-B111) for PCB design and testing conditions. There are several studies about the board level drop reliability of electronic products to focus on the solder joint failure mechanism (e.g., the crack location and characteristics) under the JEDEC standard. However, the literatures lack a study of the correlation of the PCB dynamic strain and solder joint stress during the board level drop impact and real product system level shock test. In this work, a 15x15 mm2 Quad Flat No Leads (QFN) package which is Wi-Fi module function used in industry scanner product was chosen to measure the peak acceleration and PCB strain under 1.2 meter height system level free drop. The maximum PCB strain would be used to correlate with standard board level drop tests to measure and calculate acceleration response. From the result, it shows that at similar PCB strain response the system level free drop tests peak acceleration is about 2900G and the board level drop tests peak acceleration is about 325G.Besides, the 3D transient numerical model based on the support excitation scheme was also performed to obtain thorough understanding of structural responses of the test vehicle and reliability of its solder joints under different test conditions. This model would be used to compute solder joint maximum interfacial normal and shear stresses. A fatigue reliability model that predicts the drop counts for different drop test conditions of JEDEC drop test condition: B (1500 G; 0.5 ms) and system-like condition: (325 G; 0.576 ms) was established. This study provides an accurate and reliable way to understand the correlation between system level and board level drop tests solder joint stress and to help to achieve service life improvements in early development stage.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"90 1","pages":"1509-1516"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78109519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Copper Wire Material Additive Elements to the Reliability of Wire Bonded Contacts","authors":"R. Klengel, S. Klengel, J. Schischka, T. Stephan, M. Petzold, M. Eto, N. Araki, Takashi Yamada","doi":"10.1109/ectc32862.2020.00127","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00127","url":null,"abstract":"During the past ten years, copper (Cu) bond wires have extensively replaced gold (Au) wire materials. While this development began in the consumer electronics sector, Cu wires are now increasingly advancing into applications with challenging environmental conditions and high reliability requirements, such as the automotive sector. Typically, core material of Cu wire (bare Cu / palladium coated Cu wire - PCC) is 99.99wt% Cu. In order to apply PCC wire to automotive devices, the wire material must meet the demands for long term reliability specific to automobile including stable operation under harsh environment. To achieve this, bonding wire suppliers use small amounts of additive elements in Cu core to enhance the long-term reliability.In the meantime, several types of high reliability Cu wires are available in the market. However, there are only few papers describing/comparing the effect of the additive elements used. The mechanism and progress state of degradation behavior (corrosion) depend on the type of additive element, especially for severe high temperature storage life (HTS) test. Therefore, it is very important to understand the effect of additive elements.We investigated the degradation mechanism of Cu wire bond contacts with different type of additive elements. Subsequently to challenging artifact-free preparation routines, high resolution analyzes (SEM, transmission electron microscopy - TEM, nano-spot EDS, electron beam diffraction - EBD) were carried out on ball and stitch bond contacts to clarify the effect caused by the additives. Mechanical bond tests (pull test) were also performed, and the correlation to the result of micro-structural analyzes were studied. The results of this investigation will be valuable information for the wire users in selecting the optimal wire material required for automotive devices.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"37 1","pages":"774-781"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82302057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid package for high performance Inertial Measurement Units","authors":"M. Del, A. Gritti, Douglas Lodgson, D. Cheng, N. Manca, R. Duca, T. Lao, Yiyi Ma","doi":"10.1109/ectc32862.2020.00075","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00075","url":null,"abstract":"In the field of MEMS sensors, package plays a primary role since it strongly affects device behavior and performance. Depending on the application and mission profile, design and package technology need to be targeted in order to fit the best the given requirements.When sensors work in harsh environments like in automotive applications, system is subject to very aggressive thermal cycles. Neglecting cost aspects, main and conflicting features are electrical performance stability and package board level reliability.Due to the high mechanical stiffness and due to the coefficient of thermal expansion matched versus that of silicon, ceramic cavity packages limit the stress transfer to the MEMS sensor ensuring high performance in terms of stability. However, the substantial mechanical proprieties discrepancy compared to that of PCB, implies stress absorption at solder joint level causing reduced board level reliability performance. Cavity packages based on organic substrate, show opposite behavior. If on the one hand they shift the stress concentration toward the substrate increasing board level reliability, on the other they worsen package-to-MEMS decoupling and thus the stability performance.In this paper a hybrid package is presented to achieve optimal trade-off between stability and reliability requirements. Proposed solution is based on a Si-interposer glue-bonded on the substrate, ASIC and MEMS dice are attached on top of it. Si-interposer provides stiff substrate with low coefficient of thermal expansion ensuring package-to-MEMS decoupling. Organic substrate shifts stress concentration to the interposer DA material increasing board level reliability performance.Numerical analysis has been performed to properly design the package. Focus is given to solder joint reliability at the thermal cycles. Experimental solder joint reliability test and electrical performance characterization are finally presented to confirm the effectiveness of the proposed approach.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"425-431"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78463819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Face to Face Hybrid Wafer Bonding for Fine Pitch Applications","authors":"D. Fisher, S. Knickerbocker, Daniel Smith, R. Katz, J. Garant, J. Lubguban, V. Soler, N. Robson","doi":"10.1109/ectc32862.2020.00099","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00099","url":null,"abstract":"This work demonstrates face-to-face hybrid wafer bonding at GLOBALFOUNDRIES, including fine pitch characterization and processing, along with preliminary reliability results. Bonding alignment data analysis is shown, as it is imperative to have high bonding alignment in order to assure full yield of the fine pitch interconnects. As a preliminary proof- of-concept check, simple device test data is shown as a way to electrically analyze the bond quality. Limited thermal stress testing results for reliability (utilizing JEDEC-type standards) are shown as well, proving a robust build quality.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"39 1","pages":"595-600"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76523452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine-Pitch Interconnection and Highly Integrated Assembly Packaging with FOMIP (Fan-out Mediatek Innovation Package) Technology","authors":"I. Hsu, Chi-Yuan Chen, Stanley Lin, Ta-Jen Yu, M. Hsieh, K. Kang, S. Yoon","doi":"10.1109/ectc32862.2020.00142","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00142","url":null,"abstract":"The market for mobile data access devices connected to a virtual cloud access point is exploding and driving both increased functional convergence as well as increased packaging complexity and sophistication. This is driving an unprecedented demand to increase the variety of advanced packages, such as chiplets and TSV (Through Silicon Via) interposer packaging solutions. It is expected that the industry will see more exciting interconnect technologies of advanced wafer level packaging such as TSV, 2.5D interposers, TSV-less (die last), eWLB (embedded Wafer Level Ball Grid Array)/FOWLP (Fan Out Wafer Level Package) to meet these needs. Because demands of die size reduction, efficiency enhancement and lower power consumption are always required in mobile communication applications with advanced Si node, much finer line width/space (LW/LS) and die pad pitch design is utilized. However, when the finer LW/LS design is used in the advanced Si node electronic devices, not only will there be an increased cost, but also the substrate manufacturing capability in a flip chip package must be considered. The substrate technology with finer LW/LS of 5/5μm and below currently is still a tough challenge in manufacturing. Therefore, in order to deliver a cost-efficient, fine pitch interconnection, highly integrated and performance packaging solution, the FOMIP (Fan-out Mediatek Innovation Package) technology is introduced in this paper. The FOMIP technology adopts 2.5D eWLB and flip chip package technologies with the design of 60μm die pad pitch, 5/5μm LW/LS and 1 layer redistribution layer (RDL) to extend the interconnection pitch as minimum 80μm by Cu pillar bumping process. The assembly challenges and process development including how to optimize the equipment handling and the warpage characterization of molded wafer is present. The warpage of molded wafer with Cu pillar bumps is collected to analyze different processes before eWLB package singulation. The molded eWLB package is adopted as a flip chip die to attach on a 2-layers embedded trace substrate (ETS) with LW/LS of 10/10μm by using cost-effective mass reflow (MR) chip attach process. To examine the quality and yield of the structure, package level long-term reliability tests are performed. Based on these results, it is believed that this examined FOMIP technology can be a robust, low profile and cost-effective package solution when much finer LW/LS and pitches in the die level design are utilized, such as 40μm die pad pitch with 2/2μm LW/LS and 1 layer RDL design and below.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"99 1","pages":"867-872"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79266263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Damage Accumulation in Printed Interconnects on Flex Under Combinations of Bending and Tension with Different Amplitudes","authors":"R. Sivasubramony, M. Alhendi, M. Kokash, M. Yadav, A. Raj, S. Thekkut, E. Enakerakpo, N. Adams, P. Borgesen, M. Poliks","doi":"10.1109/ectc32862.2020.00196","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00196","url":null,"abstract":"The life of a flexible hybrid electronics (FHE) product under realistic use conditions may often be limited by fatigue of the interconnects between components. This is especially true for printed traces on flex. Even if the product is only intended for use for a short time, so that accelerated testing is not required, common test protocols tend to miss critical interactions between sequential strain amplitudes, strain rates and dwells, and/or between different loading modes. Indications are that this may lead the ‘worst-case’ life to be less than anticipated by an order of magnitude or more.A comprehensive ongoing study is characterizing the behavior of different screen printed inks on TPU, PET and Kapton with and without encapsulants, as well as laser and thermally sintered aerosol jet printed nano-Ag and nano-Cu traces on Upilex and Kapton. While many details are unique to a particular combination of trace and substrate a generic picture is emerging.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"315 6 1","pages":"1225-1233"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79563482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of Electromigration Failure in Solder Interconnects under Low Frequency Pulsed Direct Current Condition","authors":"Y. Kim, Allison T. Osmanson, Hossein Madanipou, C. Kim, P. Thompson, Qiao Chen","doi":"10.1109/ectc32862.2020.00119","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00119","url":null,"abstract":"This paper concerns the electromigration (EM) failure mechanisms in solder interconnects under low frequency pulsed direct current (DC) conditions. In our study, the accelerated EM tests of Wafer-level Chip Scale Package (WCSP or WLCSP) samples are conducted under 4 different pulsed DC conditions: 0.1 Hz pulsed DC with duty factors (DFs) of 33%, 50%, 75%, and 100% (DC). The result of our testing suggests that there are at least two competing factors affecting the failure rate in an opposite manner under pulsed DC EM conditions. Specifically, when compared with the cumulative damage model (estimates the damage only during the on period), the failure kinetics is found to be more accelerated at high DF and decelerated at a lower DF. This conclusion is drawn from the observation that the EM failure rate shows an extremely nonlinear relationship with the DF and also that the failure occurs faster under a high DF than under solely DC conditions, which is not possible without a mechanism assisting the EM failure. Furthermore, it is found that there is a 2- stage resistance change before EM failure, an indication of the change in the dominant failure mechanism. The results may indicate that the pulsed DC effect on the EM failure mechanism is far more complex than anticipated with the possible involvement of a damage mechanism other than EM such as thermal fatigue.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"289 1","pages":"723-728"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76745708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect Localization in Through-Si-Interposer Based 2.5D ICs","authors":"Sajay Bhuvanendran Nair Gourikutty, Yew Meng Chow, J. Alton, Ratan Bhimrao Umralkar, Haonan Bai, Kok Keng Chua, S. Bhattacharya","doi":"10.1109/ECTC32862.2020.00189","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00189","url":null,"abstract":"Advanced packaging solutions using Through Silicon Interposers (TSI) are an attractive option to create 2.5D ICs. In many applications such as GPU and FPGA, 2.5D ICs can overcome the power, performance, and form-factor limitations of traditional IC packages. Investigating yield-loss and reliability mechanisms of such packages is made particularly challenging by the multitude of possible failure locations such as in TSV, micro-bumps, underfill, solder ball joints and RDL layers. Existing electrical and physical failure analysis tools do not have adequate resolution to accurately localize the failure in 2.5D IC. In this paper, we present a non-destructive methodology to carry out the failure analysis by localizing the defects which are entirely internal to the package and inaccessible from the exterior. In a through silicon interposer based FPGA package, a short failure has been successfully located with an accuracy of less than 10μm without the need for any sample preparation. The testing, fault localization and physical failure analysis of advanced package demonstrated here will provide a cost-effective method for improving manufacturing yield.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"128 1","pages":"1180-1185"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74277269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LTCC PoP Technology-Based Novel Approach for mm-Wave 5G System for Next Generation Communication System","authors":"S. Singh, T. Kukal","doi":"10.1109/ectc32862.2020.00307","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00307","url":null,"abstract":"This paper presents a comprehensive 5G system design methodology targeting 1Gbit/s next-generation, cellular communication based on Low-Temperature Co-fired Ceramics (LTCC), Package on Package (PoP) solution for mm wave module at 28-GHz in 5G communication System. The tile type package contributes to a dramatic reduction in size of the 5G communication system in single package along with the obvious merit of ceramic housing, which is better consistency of Coefficient of Thermal Expansion (CTE), compared to the traditional combination of ceramic board and metal housing. In addition, the paper presents the schematic diagram of heterogenous integration into an LTCC package including MMIC and RFIC (TX/RX) and 5G modem package mounted on LTCC base package and proposes a novel vertical interconnection based on Ball Grid Array (BGA) to connect vias in the lid and those in the stage of the main LTCC pan. This transition provides excellent signal integrity at high-speed data rates up to 28 Gbits/s.The paper also investigates the timing budget of TX/RX (at 28GHz) mm-wave signals in PoP technology for integrating a MMIC, PMIC, RFIC and 5G modem IC on another package. It starts by examining the package electrical modeling methodology used in GHz I/O device modeling in a more robust and accurate way to support high-volume manufacturing and high signal quality. This is followed by frequency and time domain analysis of package models to determine the optimized design parameters to achieve good signal performance.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"1973-1978"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75350323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}