冲击试验下系统级焊点应力分析

Hsin-Chih Shih, HowardTW Liao, Ryan Chen, York Liao, D. Tarng, C. Hung
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引用次数: 0

摘要

电路板水平跌落冲击测试,以评估电子封装安装在印刷电路板(PCB)焊点的可靠性是至关重要的,特别是对于手持和移动消费产品。标准跌落测试参考JEDEC规范(JESD22-B111)的PCB设计和测试条件。关于电子产品板级跌落可靠性的研究较多,主要集中在JEDEC标准下焊点的失效机理(如裂纹的位置和特征)。然而,文献缺乏对电路板水平跌落冲击和实际产品系统水平冲击试验中PCB动态应变与焊点应力相关性的研究。在这项工作中,选择了一个15x15 mm2的Quad Flat No Leads (QFN)封装,这是工业扫描仪产品中使用的Wi-Fi模块功能,用于测量1.2米高度系统水平自由下落下的峰值加速度和PCB应变。最大PCB应变将用于与标准电路板水平跌落试验相关联,以测量和计算加速度响应。结果表明,在相似的PCB应变响应下,系统级自由落体测试峰值加速度约为2900G,板级落体测试峰值加速度约为325G。此外,还建立了基于支架激励方案的三维瞬态数值模型,以全面了解试验车辆在不同试验条件下的结构响应及其焊点可靠性。该模型可用于计算焊点的最大界面法向应力和剪应力。JEDEC跌落试验工况B (1500 G);0.5 ms)和系统样条件:(325 G;0.576 ms)。本研究提供了一种准确可靠的方法来了解系统级和板级跌落测试焊点应力之间的相关性,并有助于在早期开发阶段实现使用寿命的提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Package on System Level Solder Joint Stress Analysis Under Shock Test
Board level drop impact tests to evaluate electronic package mounts on printed circuit board (PCB) solder joint reliability is critical, especially for handheld and mobile consumer products. Standard drop tests refer the JEDEC specification (JESD22-B111) for PCB design and testing conditions. There are several studies about the board level drop reliability of electronic products to focus on the solder joint failure mechanism (e.g., the crack location and characteristics) under the JEDEC standard. However, the literatures lack a study of the correlation of the PCB dynamic strain and solder joint stress during the board level drop impact and real product system level shock test. In this work, a 15x15 mm2 Quad Flat No Leads (QFN) package which is Wi-Fi module function used in industry scanner product was chosen to measure the peak acceleration and PCB strain under 1.2 meter height system level free drop. The maximum PCB strain would be used to correlate with standard board level drop tests to measure and calculate acceleration response. From the result, it shows that at similar PCB strain response the system level free drop tests peak acceleration is about 2900G and the board level drop tests peak acceleration is about 325G.Besides, the 3D transient numerical model based on the support excitation scheme was also performed to obtain thorough understanding of structural responses of the test vehicle and reliability of its solder joints under different test conditions. This model would be used to compute solder joint maximum interfacial normal and shear stresses. A fatigue reliability model that predicts the drop counts for different drop test conditions of JEDEC drop test condition: B (1500 G; 0.5 ms) and system-like condition: (325 G; 0.576 ms) was established. This study provides an accurate and reliable way to understand the correlation between system level and board level drop tests solder joint stress and to help to achieve service life improvements in early development stage.
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