2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Viscoelastic Modeling for Heterogeneous Fan-out Wafer Molding Process","authors":"S. Yeh, P. Lin, K. C. Lee, M. Yew, C. C. Yang, J. H. Wang, C. Hsu, P. Lai, Dion Tseng, S. Cheng, S. Jeng","doi":"10.1109/ECTC32862.2020.00174","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00174","url":null,"abstract":"Fan-out wafer level package (FOWLP) is a disruptive technology in the semiconductor packaging industry. Demand for higher system performance has caused an increase in both package size and the complexity of heterogeneous integration. Large warpage, which arises from significant volume changes in molded underfill (MUF) during the curing and subsequent assembly processes, is a top process and reliability issue.The selection of molding material is critical importance in FOWLP, as the material must meet multiple manufacturing requirements. In this study, an integrated modeling approach is used to predict fan out wafer form warpage. This approach considers both chemical shrinkage and cure dependency of molded underfill. Viscoelastic relaxation behavior over the course of compression molding cured (namely CMC) and post molding cured (namely PMC) has been carefully modeled. Measurements of material properties used in our models were characterized through differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA). The result of our integrated modeling approach was validated by comparing actual warpage data of various temperature loading conditions. Predicted warpage values are in good agreement with in-line experimental data.Furthermore, we apply this methodology to study the wafer fan-out ratio and Cu density effect. It is shown that Cu density effect is not sensitive, and higher wafer fan-out ratio induces larger warpage due to more molding volume.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"51 1","pages":"1081-1086"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81109702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermomechanical Deformations of Power Modules with Sintered Metal Buffer Layers under Consideration of the Operating Time and Conditions","authors":"A. Schiffmacher, J. Wilde, Carsten Kempiak, A. Lindemann, J. Rudzki, F. Osterwald","doi":"10.1109/ectc32862.2020.00094","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00094","url":null,"abstract":"In this work an investigation of the thermomechanical deformation behaviour of power modules with sintered metal buffer layers is presented under consideration of the operating time. The thermomechanical deformation is measured during active operation of the device using an optical measurement technique. The in-plane strain and the out-of-plane curvature were evaluated in dependency of the temperature by applying different operating conditions (IC, ton, toff). In addition, comparisons of the deformations of modules are shown, which on the one hand were measured directly after the production and on the other hand have passed through several thousand active load cycles until the end-of-life (EOL). Furthermore, the relevant electrical and thermal parameters (VCE,Sat, Tvj,max, ΔTvj, Rth) were recorded during the load cycles in order to analyse the failure mechanisms. The evaluation of the electrical measurement with regard to the failure mechanism correlates with the findings of the thermomechanical deformation. The uncertainty regarding the primary failure mechanism, which exists when evaluating only VCE and Rth, can be eliminated with the additional optical method without destroying the test module.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"561-567"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85432750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"OpenCAPI Memory Interface Simulation and Test for Differential DIMM Channel with SNIA SFF-TA-1002 Connector","authors":"Biao Car, J. Hejase, Kevin Mcilvain, Kyle Giesen, Zhaoqing Chen, Hongqing Zhang, Junyan Tang, Megan Nguyen, Devon Baughen, D. Dreps, Brian Connolly, Glen A. Wiedemeier, D. Becker, S. Chun, B. Beaman, Zhineng Fan, Yifan Huang, A. Wander, Victor Mahran","doi":"10.1109/ECTC32862.2020.00158","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00158","url":null,"abstract":"DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate per data differential pair being specified at 25.6Gb/s minimum at present and at 51.2Gb/s maximum in the future. This is a significant data rate increase for DRAM modules over conventional single-ended data transferring DIMMs. For example, the DDR5 LRDIMM data transfer rate per pin is 3.2Gbps. This study utilizes the DDIMM early engineering samples with DDR4 to evaluate the OMI channel running at 25.6Gb/s.Validating the DDIMM PCB wiring for the high-speed differential memory bus requires accurate high-speed link simulations. These simulations require accurate models representing differential wiring in the DDIMM PCB stack up. The models must be built using not only representative physical dimensions but also accurate frequency dependent material properties obtained through PCB characterization. The simulation results of the initial study in 2018-19 concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate[l]. This paper is based on 2019-20 DDIMM test results and the full channel time domain eye diagram analysis with BER at 10˄-15 assuming an improved DDIMM PCB stack up with hybrid structure to satisfy signal integrity while minimize the material cost premium.DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector which differs significantly from the JEDEC RDIMM connector for improved electrical signaling characteristics. The connector to PCB interface design has been studied as it is of utmost importance for achieving good signal integrity[l]. The DDIMM test samples for this study include the high speed connector to PCB interface attributes such as Plated Through Hole (PTH) in ground contact pad, ground plane void under OMI signal pad and tie bar removal.The challenges of DDIMM PCB mechanical interaction with SFF-TA-1002 connector have been highlighted in the initial study[l]. This study uses early engineer samples to evaluate the insertion/extraction performance. Future work will use test vehicle of PCB/connector pairs to characterize the high speed electrical performance and evaluate the contact reliability.In summary, this paper presented the full channel simulation result assuming an improved DDIMM PCB material/stack-up at 25.6Gbps for comparison with the performance that baselined in the initial work with the industry standard PCB material. Physical characterization of the engineering samples has been conducted to baseline the DDIMM PCB to connector contact interface. Electrical test is performed with early engineering samples in IBM high speed system to verify the simulation result.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"970-978"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79926803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra High Density SoIC with Sub-micron Bond Pitch","authors":"Y. H. Chen, C. A. Yang, C. Kuo, M. F. Chen, C. Tung, W. Chiou, Douglas C. H. Yu","doi":"10.1109/ECTC32862.2020.00096","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00096","url":null,"abstract":"An ultrahigh density 3D technology, SoIC_UHD, with sub-micron pitch inter-chip vertical interconnect enabling a density ≥ 1.2 million bonds/mm2 is reported for the first time. Proven yield and reliability of SoIC_UHD are demonstrated with a foundry front-end wafer level 3D heterogeneous system integration (WLSI) platform. SoC deep partitioning into mini chiplets with SoIC_UHD can extend Moore's Law for longer term than that achieved by conventional 3DIC stacking with micro-bumps. Microsystem scaling, which is complementary to transistor scaling, can continue to improve transistor density, system PPA, and cost competitiveness.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"143 1","pages":"576-581"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77024103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive Shot Technology To Address Severe Lithography Challenges For Advanced FOPLP","authors":"John F. Chang, K. Best, Jian Lu, Burhan Ali, Mike Marshall","doi":"10.1109/ECTC32862.2020.00150","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00150","url":null,"abstract":"Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Développement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014, validating the market requirement for fan out packaging. While FOWLP has been used for many years, there is still a relentless drive to reduce the cost, and fan-out panel level packaging (FOPLP) has been proposed as one possible solution. FOPLP allows users to put more chips on a substrate, meaning more product output and a higher substrate utilization percentage. According to Yole’s analysis, the FOPLP market size will increase to $2.79 hundred million with 79% CAGR, showing that more people are adopting FOPLP.FOPLP has many advantages and low cost potential, but it faces significant process challenges, such as die placement error and substrate warpage control. One of the key challenges is the trade-off between overlay, yield, and throughput during the lithography processing steps. A user exposes multiple dies per exposure shot to increase throughput, but this can result in lower overlay yield because of \"pick and place\" die placement error. To overcome the low yield issue, each die needs to be aligned, but this impacts throughput, so a compromise is required. To find the balance point between throughput and overlay is one of the biggest challenges for FOPLP.In this paper we address the tradeoff between throughputs and overlay yield, we demonstrate an integrated feedforward adaptive shot solution. This feedforward approach uses a third party metrology system to measure reconstituted panel die location data and sends the data to the stepper via a network. With feedforward algorithm technology, the stepper uses smart adaptive shot technology to generate an optimized variable shot size layout. This layout ensures the overlay yield is within specification with the minimum number of exposure steps. With feedforward adaptive shot technology, the user can maximize the throughput of the stepper and ensure the overlay yield at the same time.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"918-923"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82271861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of package-level EMI shielding using conformally coated conductive and magnetic materials in low and high frequency ranges","authors":"Kisu Joo, Kyu Jae Lee, Hyun Jun Sung, Seung Jae Lee, Se Young Jeong, H. Park, Yoonhyun Kim","doi":"10.1109/ectc32862.2020.00107","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00107","url":null,"abstract":"The magnetic permeability and thickness of magnetic films and their effects on the EMI shielding effectiveness at 1 MHz were investigated. Various kinds of magnetic films having a thickness of 100μm~500μm and a permeability of 50μ~300μ were fabricated. 2D and 3D test vehicles were employed for measuring near-field EMI shielding effectiveness under magnetic source condition. By utilizing 2D and 3D test vehicles, the effects of various magnetic materials on the near-field EMI shielding effectiveness under H-field sources were studied at a low frequency of 1MHz. As a result, we found that the reduction rate of H-field SE is 8.57%, which is very similar to the total opening area of the four sides. the near H-field SE is affected as a logarithmic function of permeability and thickness equally","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"57 1","pages":"647-652"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87838158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Combined peridynamic theory and kinetic theory of fracture for solder joint fatigue life prediction","authors":"E. Madenci, C. Diyaroglu, Y. Zhang, F. Baber, I. Guven","doi":"10.1109/ectc32862.2020.00049","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00049","url":null,"abstract":"This study presents an approach that combines the kinetic theory of fracture with peridynamic theory to predict solder joint fatigue life in electronic packages. It is applied to two different package types whose measured life values are reported in literature. The nonlinear finite element analyses of the global package model and sub-model of the critical joint provide the boundary conditions for the peridynamic model. Both the finite element and peridynamic analyses are performed in the ANSYS framework by using the available elements and options. This new approach captures the experimentally observed damage topology in a solder joint. Although the initial and final fatigue life predictions are acceptable, the predictions can certainly be improved with accurate values of activation energy and activation volume for materials employed in the package.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"77 1","pages":"236-248"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86930667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Mechanics Model for the Moisture Induced Delamination in Fan-Out Wafer-Level Package","authors":"T. Chiu, Ji-Yen Wu, Wei-Te Liu, Chang Liu, Dao-Long Chen, M. Shih, D. Tarng","doi":"10.1109/ECTC32862.2020.00193","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00193","url":null,"abstract":"The effect of moisture absorption on the risk of interface delamination in a fan-out (FO) wafer level package (WLP) was investigated by using experimental and numerical analyses. A double-cantilever-beam (DCB) fracture mechanics test was applied to quantify the degradation of interfacial debonding resistance due to moisture exposure. The driving forces of delamination on various interfaces in the FO WLP were evaluated by using a coupled hygro-thermo-mechanical model. The moisture diffusion related material models such as diffusivity, saturation concentration and the hygroscopic swelling of the polymer constituents in the FO package were characterized experimentally and implemented in the numerical stress model. The numerical model was applied to evaluate the transient stress evolutions at critical locations around the corners of the Si die during moisture sensitivity tests. It was observed that the moisture absorption degrades adhesion significantly. It also leads to a change in stress state around the corners of Si die from compression to tension, and as a result, significantly increase the risk of delamination.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"33 1","pages":"1205-1211"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87077345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedded 3D-IPD Technology based on Conformal 3D-RDL: Application for Design and Fabrication of Compact, High-Performance Diplexer and Ultra-Wide Band Balun","authors":"A. Ghannam, A. Magnani, D. Bourrier, T. Parra","doi":"10.1109/ECTC32862.2020.00292","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00292","url":null,"abstract":"In this paper, an embedded 3D-IPD technology based on conformal 3D-RDL that yields high performance, small-size and low-cost devices is presented. The technology relies on high-Q thin film capacitors and 3D inductors as well as on thru-mold-vias (TMV) and mold compound to form a surface mount 3D-IPD device (SMD). We demonstrate how to form TMVs simultaneously with 3D-inductors using 3D-RDL technology. Hence, no laser drilling nor tall Cu vias electroplating are required.A WLAN diplexer (2.4 & 5GHz) and an UWB balun (1.4 – 3GHz) where synthesized, fabricated and measured to demonstrate electrical performance of this technology. We first report the impact of 3D inductor’s Q-factor on electrical performance of these devices and how to use this data to accurately assess real-life performance of inductors. Then, we demonstrate that low-loss (0.3dB and 0.56dB), high attenuation (24dB and 28dB) and high isolation (25dB and 29dB) are achieved for a 0.38mm2 3D diplexer. Whereas, an insertion loss <0.85dB, amplitude unbalance <0.5dB and phase unbalance <3° are achieved for 2.5 mm2 UWB balun. Reliability result is also presented here.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"1867-1874"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87102596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of solder interconnect configurations and performance of vertical laser assisted assembled “3.5D” packages","authors":"Andrej Kolbasow, Matthias Fettke, Timo Kubsch, Vinith Bejugam, T. Teutsch","doi":"10.1109/ectc32862.2020.00302","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00302","url":null,"abstract":"The current study explains the performance of different solder interconnections (SAC305, SnPb, SnBi) associated with horizontal and vertical laser soldering in a 3.5D semiconductor package, using laser assisted bonding (LAB). In a 3.5D package, a device can be vertically bonded to the side of a 3D stack, thus enabling connection of different substrates to the stack. For a wide range of applicability, solder balls with high and low melting points, and varying solder compositions were selected, their corresponding laser reflow characteristics were recorded and analyzed. The metallurgical properties of the solder interfaces were analysed, in detailed pre- and post-thermal cycling tests using a focused ion beam (FIB), scanning electron microsope (SEM) and x-ray. The mechanical strength of the solder interconnections prior to assembly was measured using a shear test unit, and the corresponding fracture modes were inspected using an optical microscope. Moreover, real-time performance of 3D and 3.5D packages will be correlated with in silico electrical results based on the evaluated solder alloy SAC305. Finally, potential photonic applications of 3.5D optical packages, and future prospects concerning intended reliability and stability are highlighted.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"1936-1942"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87551328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}