2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Cap Fabrication and Transfer Bonding Technology for Hermetic and Quasi Hermetic Wafer Level MEMS Packaging","authors":"K. Zoschke, P. Mackowiak, Kevin Kröhnert, H. Oppermann, N. Jürgensen, M. Wietstruck, A. Göritz, S. Tolunay Wipf, M. Kaynak, K. Lang","doi":"10.1109/ECTC32862.2020.00076","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00076","url":null,"abstract":"This article describes a new wafer level capping technology for hermetic or quasi-hermetic 1st level device sealing. The technology is based on fabrication of cap structures with bond frames and optional recesses at temporary carrier wafers and their subsequent transfer bonding to the device wafer. The final release of the caps from the carrier wafer is obtained by laser assisted de-bonding. The cap fabrication relies on deposition and structuring methods from advanced packaging featuring mask aligner lithography for pattern definition. Based on that, bond frames and also the cap outlines can be defined almost freely by layout and thus, fully arbitrary shaped cap structures with irregular forms, sizes and locations and with irregular pitch become possible. The bond frames can be made of adhesive, metal or metal with solder cap to provide just mechanical or air tight device sealing to the target wafer. Since the caps are formed from a wafer, which is bonded to a carrier wafer, even fabrication of ultra-thin caps in the range of 50 μm or less is possible by adding related grinding and polishing steps. For the transfer of the caps to the device wafers, so-called donor wafers are used which can be handled with standard wafer-to-wafer alignment and bonding equipment. Due to the toughness of the temporary adhesive, which holds the caps on the carrier, wafer bonding processes under vacuum with temperatures up to 370 °C and pressures in the MPa range can bet utilized for the cap transfer bonding.The technology was applied for quasi-hermetic sealing of RF-MEMS switches on 200 mm BiCMOS wafers using adhesive bond frames as well as for hermetic sealing operations on 200 mm test wafers and on 200 mm MEMS wafers using soldering of AuSn bond frames. The related cap fabrication and bonding processes as well as associated results are described in this paper.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"133 1","pages":"432-438"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77211435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A highly reliable die bonding approach for high power devices by low temperature pressureless sintering using a novel Cu nanoparticle paste","authors":"Hai-Jun Huang, X. Wu, Min-bo Zhou, Xin-Ping Zhang","doi":"10.1109/ECTC32862.2020.00266","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00266","url":null,"abstract":"A novel Cu nanoparticle (NP) paste with the capability of pressureless sintering at low temperature in nitrogen is developed using a type of easily synthesized Cu NPs. The feature of bimodal size distribution of Cu NPs can be inherited to the Cu NP paste, which facilitates the formation of dense as-sintered microstructure, mainly consisted of Cu bulks, in sintered joints. The optimization of the sintering process condition has been achieved by using Taguchi method, and so-obtained Cu paste joints show shear strength as high as 65.24 MPa. Moreover, the formulation of the solvent containing ethylene glycol (EG) and glycerol with an optimized weight ratio, which is employed for preparation of the Cu NP paste, has also been demonstrated to be crucial for the formation of Cu bulks in joints and so-induced superior bonding strength. Finally, the results of high temperature storage (HTS) tests of Cu paste joints after aging at 200 °C for 600 h show that there is a slight degradation of bonding strength of joints, mainly due to the generation of voids at the Cu-paste/Cu interface.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"46 1 1","pages":"1697-1702"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77475853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid Fan-out Package for Vertical Heterogeneous Integration","authors":"Po-Yao Chuang, M. Lin, Shih-Ting Hung, Y.-W. Wu, D. Wong, M. Yew, C. Hsu, L. Liao, P.-Y. Lai, P.-H. Tsai, S.M. Chen, S. Cheng, S. Jeng","doi":"10.1109/ectc32862.2020.00061","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00061","url":null,"abstract":"A new ultra-thin high-density hybrid package that combines fan-out RDL with a backside laminated interposer is developed for mobile applications. The package features up to six fan-out RDL layers for chiplet integration and two to four routing layers in a backside interposer for a high pin-count module stacking architecture. The laminated interposer is placed conformally to the SOC to create a base package as thin as 250 um. An integration challenge in the CTE mismatch between fan-out RDL and laminated interposer is successfully resolved. For a 14x14 mm2 package, a low package warpage is achieved at RT and HT, measured at 37um and -46um, respectively. The twist index is also controlled within 30um. Despite its thinness, the new hybrid package shows enhanced mechanical strength by incorporating the laminated interposer. It is successfully demonstrated that memory and RF modules can be stacked on this thin base package using the standard production flow. The thin packages pass stringent component and board level reliability tests. The new hybrid package combines the electrical and thermal advantages of fan-out packages and the mechanical advantage of laminated interposers. This hybrid fan-out package has a very high interconnect density, which provides excellent design flexibility for advanced vertical heterogeneous integrations.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"333-338"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81215191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation into the failure mechanism of silver nanowire network film under electrical stress","authors":"Kaiqing Wang, Yunxia Jin, Xiaocun Wang, Baifan Qian, Jianzhong Wang, F. Xiao","doi":"10.1109/ECTC32862.2020.00195","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00195","url":null,"abstract":"Silver nanowire (AgNW) network film exhibits good transparency, conductivity and flexibility, which has been widely studied as the transparent electrode in electronics. The weak stability of AgNW film under electrical stress may bring about high risk of device failure, but insufficient studies have been devoted to the electrical failure mechanism of AgNW film. In this work, we investigated the failure mechanism of AgNW network film under electrical stress, and discussed the relationship between electrical stability and electrical type, current density, temperature and humidity, respectively. AgNW film exhibits much better stability under AC stress than DC stress, and electromigration has significant effect on the failure of AgNW network under DC stress. The synergistic effect of short-range electromigration and Joule heating under DC stress results in the failure mode of narrow break line in the film perpendicular to the current flow. The location of break line moves from middle area to anode side with decreased current density, attributed to the change of dominant mechanism from thermal fusing to electromigration. The electrical lifetime demonstrates exponential function relationship with temperature, and the activation energy is calculated to be 0.53 eV below 136 °C. In addition, electrochemical migration is confirmed in AgNW network failure under high humidity environment. The understanding of the electrical failure mechanism of AgNW network in multiple conditions provides reference for evaluating and improving the applied reliability of AgNW film.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"1218-1224"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81110581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation and Comparison of Aging Effects in SAC+X Solders Exposed to High Temperatures","authors":"Jing Wu, M. Alam, KM Rafidh Hassan, J. Suhling, P. Lall","doi":"10.1109/ectc32862.2020.00085","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00085","url":null,"abstract":"Microstructural evolution occurs in lead free Sn-Ag- Cu (SAC) solder joints exposed to isothermal aging. Such changes lead to degradations in the mechanical properties and creep behavior of the solder, and can result in dramatic reductions in the board level reliability of lead-free electronic assemblies subjected to aging. In our recent research, Scanning Electron Microscopy (SEM) has been used to: (1) monitor aging induced microstructural changes occurring within fixed regions in selected lead-free solder joints, (2) create time-lapse imagery of the microstructure evolution, and (3) analyze the microstructural changes quantitatively and correlate to the observed mechanical behavior evolution. This approach has removed the limitations of many prior studies where aged and non-aged microstructures were taken from two different samples and could only be qualitatively compared.In our recent papers presented at ECTC 2018 and 2019, the developed approach was used to observe the microstructure evolutions in SAC305 (96.5Sn-3.0Ag-0.5Cu) and SAC_Q (SAC+Bi) solder joint samples for up to 2000 hours of aging at T = 125 °C. In the current study, we have extended this work for longer aging times up to 7000 hours, and we have also examined microstructural changes for aging at another temperature (T = 100 °C). Finally, a more extensive study has been performed for short term aging up to 270 hours, which is when the majority of aging induced changes occur. The aging induced changes in microstructure have been correlated with the changes in mechanical behavior measured using uniaxial tensile testing.The area and diameter of each IMC particle were tracked during the aging process using the recorded images and imaging processing software. As expected, the analysis of the evolving SAC305 and SAC_Q microstructures showed a significant amount of diffusion of silver and bismuth in the beta-tin matrix during aging. In particular, Ag3Sn particles coalesced during aging leading to a decrease in the number of particles. Any bismuth in the SAC_Q microstructure was observed to quickly go into solution, resulting in solid solution strengthening. This primary occurred within the beta-Sn dendrites, but also in the Ag3Sn intermetallic rich regions between dendrites. The presence of bismuth in was also found to slow the diffusion process that coarsens the Ag3Sn IMC particles. The combination solid solution strengthening and a lower diffusion rate for Ag lead to reduced aging effects in the SAC+Bi alloy relative to the SAC305 solder alloy.The mechanical behavior degradations in the two alloys were also investigated. Before testing, the solder uniaxial specimens were aged (preconditioned) at T = 125 °C. At each aging temperature, several durations of aging were considered including 0, 2, 6, 12, and 24 hours. Uniaxial tensile tests were then performed on the aged specimens at high temperature (T = 125 °C). Using the measured data, the evolutions of the high temperature stress-strain","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"492-503"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88341404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Numerical Technique to Evaluate Warpage Behavior of Double Sided Rigid-Flex Board Assemblies during Reflow Soldering Process","authors":"C. Lau, Y. Tan, Choon Kuai Le, Ning Ye","doi":"10.1109/ectc32862.2020.00093","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00093","url":null,"abstract":"High-performance computing and data center demands for complex form factor solid state drives (SSD) are driving the use of thinner electronic components and double-sided printed circuit board (PCB) in the assembly process. The use of thinner and multiple rigid-flex panel-level PCBs has led to warpage issues in the surface mount technology (SMT) assembly process, which in turn impacts the board assembly quality and yield performance. The selection of rigid-flex PCB/panel design, component density, and reflow thermal profile can affect warpage behavior during reflow soldering leading to SMT assembly defects, such as pad cratering, joint cracking, and open joint. The aim of this work is to provide a comprehensive board level assessment by considering those selection parameters before mounting packages on rigid-flex PCB. Residual strain from reflow process plays a role in the stress generated in the finished product, especially for double-sided SMT assembly. It is therefore important to consider the SMT process sequence in numerical modeling. A strategy of using imported trace on rigid-flex PCB coupled with element birth and death technique to simulate the effect of double sided SMT is outlined. Through the simulation results, it is apparent that the warpage behavior has a strong correlation with the SMT process sequence. Results demonstrate the excellent capability of the proposed modeling tools for identifying the excess warpage of PCB assembly. Implementation of the proposed pallet design will help to address the double-sided rigid-flex board warpage issue, and improve yield performance. The proposed approach greatly reduces evaluation time, shortens product life cycle development, and is more cost effective to address quality issues.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"160 1","pages":"554-560"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77610422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design, fabrication and characterization of a Q-band patch antenna integrated on stacked interposers","authors":"Yunheng Sun, Yufeng Jin, Tingting Lian, Shengli Ma, Yuchi Yang, Wei Wang, Liu-lin Hu, Shuwei He","doi":"10.1109/ECTC32862.2020.00347","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00347","url":null,"abstract":"In this study, we present a Q-band patch antenna with an underling cavity integrated on the stacked high-resistivity Si interposers. A process is developed and sample is fabricated. Evaluation is done and the measurement results shows that it has an operating frequency of 32.75GHz, a –10dB bandwidth of 1.04GHz, a maximum gain of 3dB. Those results prove the feasibility of integrating high-frequency antennas with TSV interposer preliminary.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"10 1","pages":"2230-2235"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87659873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Integrity Performance Gain of a Novel Integrated Stack Capacitor (ISC) Solution for High-end Computing Applications","authors":"Eunseok Song, D. Oh, S. Cha, Jae-gwon Jang, Taejoo Hwang, Gyoungbum Kim, J. Kim, S. Min, Kilsoo Kim, Dae-woo Kim, Seung-Bum Yoon","doi":"10.1109/ectc32862.2020.00215","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00215","url":null,"abstract":"An integrated stack capacitor (ISC) solution, which can effectively suppress power noise in high frequency bands, is introduced. The basic structure of the ISC is a vertical cylinder array consisting of many capacitive vias. The proposed ISC shows high capacitance density compared to the existing silicon capacitors. In this study, the power integrity (PI) performance gain of the proposed ISC solution was analyzed by applying it to the advanced package platforms such as 2.5D silicon interposer, fanout (FO) package, RDL interposer, and substrate based chiplet. Based on 3D wafer on wafer (WoW) technology, ISC is a not only 2.5D silicon interposer for high performance computing (HPC) and server that operates with high power, but also a novel silicon capacitor solution that can be applied to substrate and fanout packages for mobile and automotive.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"1358-1362"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90280598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Complex Permittivity Measurements in a Wide Temperature Range for Printed Circuit Board Material Used in Millimeter Wave Band","authors":"Kazuki Takahashi, Shunichi Kikuchi, Akiko Matsui, Mitsunori Abe, Kouhei Chouraku","doi":"10.1109/ectc32862.2020.00153","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00153","url":null,"abstract":"This paper discusses the temperature dependence of the complex permittivity in the millimeter-wave band of dielectric materials used in printed circuit boards and its transmission loss effect. In the structure of a newly developed balanced-type circular disk resonator, two dielectric material samples sandwiching a thin circular copper disk can expand and contract under uniform pressure against temperature changes, which means the frequency dependence of the complex permittivity between 10 GHz and 95 GHz can be stably measured in a temperature range from -30°C to 130°C. To confirm the validity of measured values, a printed circuit board having a transmission line with a microstrip structure was fabricated, and transmission loss was measured at room temperature. Then, the dielectric material and the copper foil were taken out, the frequency dependence was measured, and the transmission loss of the transmission line was calculated by HFSS (three-dimensional electromagnetic field analysis solver) using these measured values. In the present model, transmission loss value calculated using the measured value is 10% closer to the measured value than that using the catalog value, and almost 96% of the measured values could be fitted. The frequency dependence of other dielectric materials was measured between 10 GHz and 95 GHz at temperatures of -30°C, 25°C, and 130°C. A difference of up to 0.57 dB/cm was obtained between the transmission loss calculated from the complex permittivity of the catalog value for 10 GHz at the temperature of 25°C and the transmission loss calculated from the measured value, confirming the effect of the temperature dependence of complex permittivity.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"938-945"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91021752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Imprint-Through Mold Via (i-TMV) with High Aspect Ratio and Narrow Pitch for Antenna in Package","authors":"Xinrong Li, T. Ogawa, T. Shibata, S. Yoneda, N. Suzuki, T. Nonaka","doi":"10.1109/ECTC32862.2020.00032","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00032","url":null,"abstract":"The imprint-Through Mold Via was proposed for electromagnetic interference (EMI) shielding of Antenna in Package (AiP) application. The 300 μm-height via array could be successfully imprinted by using the silicon master which has 743 pillars with the diameter of 100 μm, pitch of 200 μm and height of 370 μm, and the via array was well filled by vacuum printing method with newly developed conductive paste utilizing transient liquid phase sintering. In order to evaluate the electric characteristics of the via array, a daisy-chain test vehicle (TV) which could connect all the vias together was fabricated. In the result of the reliability test, no electrical failure was confirmed of this daisy-chain.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"119 1","pages":"120-125"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86104233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}