2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Heterogeneous Integration Using Organic Interposer Technology","authors":"George Scott, JaeHun Bae, Kiyeul Yang, WonMyoung Ki, Nathan Whitchurch, M. Kelly, C. Zwenger, JongHyun Jeon, Taekyeong Hwang","doi":"10.1109/ectc32862.2020.00145","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00145","url":null,"abstract":"As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shift is not just to add local memory, such as the addition of high-bandwidth memory (HBM) module(s) to an application-specific integrated circuit (ASIC) die, but also to separate what would have been a monolithic ASIC in prior generations to its constituent parts, such as the central processing unit (CPU) cores, serializer/deserializer (SerDes) and input/output (I/O) blocks. By splitting the monolithic die into smaller functional blocks, costs can be reduced through improved wafer yield on the smaller CPU cores and re-using older, vetted intellectual property (IP) from a prior silicon node for the I/O and SerDes that do not necessarily need the most advanced silicon node.The traditional approach to fine-pitch multi-die packaging has been silicon interposers with Through Silicon Vias (TSVs). While the TSV approach has ushered in new performance levels never seen before, one of the major limitations is the inability to scale with higher and higher frequencies. The maximum frequency that a silicon interposer can handle between die-to-die interconnects is approximately 4 GHz due to the parasitics of the silicon. As dieto-die interconnects increase their bandwidth to higher and higher levels, the 4-6 GHz limitation can become a major bottleneck. Eliminating the silicon and silicon dioxide dielectrics and using polymers as the dielectric and the interposer itself can solve this problem.This paper will discuss how to use High-Density Fan-Out (HDFO) technology to replace the TSV-bearing silicon interposer with an organic interposer to enable higher bandwidth die-to-die interconnects for heterogeneous integration.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"40 1","pages":"885-892"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90459341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Coaxial Through-Silicon-Vias Using Low-κ SiO2 Insulator","authors":"Pengbo Yu, Hongxiao Lin, Zhi-wei He, Changmin Song, Jian Cai, Qian Wang, Zheyao Wang","doi":"10.1109/ectc32862.2020.00187","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00187","url":null,"abstract":"This paper reports the design, fabrication, and test of a novel coaxial through-silicon-via (TSV) using low-κ SiO2 insulator and fabricated on normal silicon substrate for high-frequency applications. The coaxial TSV consists of an annular Cu conductor deposited on the outer sidewall of a central Si post, an annular Cu shielding layer deposited on the inner sidewall of an annular trench that surrounds the Si post, and an annular low-κ SiO2 insulator in-between the two Cu layers. The low-κ SiO2 insulator, with the advantage of low cost and good high-frequency performance, is formed by vacuum-assisted spinfilling and thermal curing of liquid precursors. The Cu shielding layer prevents the propagation of electric fields into the lossy silicon substrate and blocks external interferences, and the low-κ SiO2 insulator reduces the dielectric loss and the parasitics of the TSVs. The measured S21 and S11 of TSVs are, respectively, -0.48 dB and -14.91 dB at 10 GHz, and are -1.48 dB and -11.73 dB at 40 GHz, indicating that the coaxial TSVs achieve excellent propagation properties at high-frequency that are impossible for normal TSVs.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"1167-1172"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90501634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical Model for Understanding Failure Mechanism of Back End of Line (BEOL) in Bump Shear","authors":"Wei Wang, Wei Zhao, Mark Nakamoto, M. Schwarz, D. He, Xuefeng Zhang, Lily Zhao, A. Syed","doi":"10.1109/ectc32862.2020.00048","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00048","url":null,"abstract":"With the increasing requirement for advanced technology nodes in high-performance devices, low-K (LK), ultralow-K (ULK) and extreme low K (ELK) dielectric materials have been integrated with copper pillar bumps in Back-End-of-Line (BEOL) interconnects in flip chips to reduce capacitance and thus resistance-capacitance (RC) delay. The dielectric materials (LK, ULK and ELK) are fragile compared to silicon oxide. Due to large coefficient of thermal expansion (CTE) mismatch between the die and substrate, dielectric crack and delamination can be induced by the stress transferred by the stiffer copper pillar bumps during chip attach reflow. It is thus important to characterize silicon BEOL strength for chip-package-interaction (CPI) qualification.Bump shear provides a quick method to characterize the silicon BEOL strength by shearing the copper pillar bumps. However, the failure mode in bump shear test is complex and poses a challenge for understanding the failure mechanism. It was observed experimentally that the failure mode induced by bump shear depends on the shear height. Generally, brittle dielectric failure can be induced with a higher shear height. In contrast, ductile Aluminum pad (AP) failure can occur with a lower shear height. A mixed failure mode of both dielectric failure and AP failure may also occur, making the failure mechanism more complex. Furthermore, it was found that metal layout in the BEOL could also affect the critical shear force in the shear load curve.This paper presents a numerical model for better understanding the failure mechanism of BEOL in bump shear. First, a stress model is developed to understand the stress distribution in bump shear. In this work, a contact/target element model is used to simulate the interaction of shear tool surface with the bump surface and a cohesive zone material (CZM) model is used to simulate the potential interface debonding. Plasticity of copper pillar is also considered to capture the plastic energy dissipation. Therefore, the bump/shear tool interaction, energy release due to crack propagation and copper plastic energy dissipation can be well captured in the model. Then an ELK fracture model is also developed to understand the BEOL crack failure. The impact of metal density on ELK crack is evaluated by comparing the energy release rate at the crack tip. The impact of dielectric material properties on the ELK crack is also evaluated. The numerical models provide a good understanding of the stress distribution and BEOL fracture mechanism in bump shear.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"229-235"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89336631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Density Embedded Electronics in Textiles with 3D Flex Package Transfer","authors":"M. Monshi, Jose-Solis Camara, S. Bhardwaj, J. Volakis, P. Raj","doi":"10.1109/ectc32862.2020.00136","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00136","url":null,"abstract":"Hybrid device-flex-textile interconnect and integration technologies were developed to realize smart wireless sensing systems. Test vehicles were fabricated to emulate high-density 3D flex packages in textiles. Representative test chips were assembled onto patterned copper traces on Liquid Crystal Polymer (LCP) flex substrates. These flex circuits were embedded into textiles with deformable silver adhesive interconnects. Fluoroelastomers were utilized as encapsulants to suppress moisture permeation and interaction with the embedded electronics. Contact resistances of the flex-to-textile and device-to-flex interconnects were investigated after fabrication, flexing, thermal and humidity treatments. DC resistances were extracted through Kelvin Probe structures and their stability during thermal and humidity exposure conditions were investigated. In addition to DC resistance, RF loss performance was also improved when we use silver adhesive interconnects to replace bulky and inflexible solder interconnects.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"70 1","pages":"835-840"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89885709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of Digital Signage Modules composed of Mini-LEDs using Laser-Assisted Bonding (LAB) Technology","authors":"Kwang-Seong Choi, Jiho Joo, Ki-seok Jang, Y. Eom, Gwang-Mun Choi, Hogyeong Yun, Seok-Hwan Moon, Jong-Sun Kim, Mingyun Oh, Ji-Hoon Choi, Ji-Woong Choi, S. Cho, Shin Choi, Sanghyun Park, Gi Cheol Kim, Sang-ki Kim, Jin Sung Kim, Sehoon Yoo","doi":"10.1109/ectc32862.2020.00167","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00167","url":null,"abstract":"Light-emitting diodes (LED) based displays are highlighted because of their interesting features compared with others. Especially, the LED display with active matrix (AM) has additional advantages such as low power consumption, elimination of current cross talk, and so on. However, AM- driving LED displays are fabricated on active substrates with transistors so that there are many problems like high-cost, difficulty in enhancing yield, and repair problem. As an alternative, an AM-driving LED display on a passive substrate has been developed in this study. One pixel is composed of RGB mini-LEDs and a control IC, fabricated using the CMOS technology. It can decrease the cost of a substrate compared with other AM LED displays, and keep constant the complexity of substrate regardless of the variations of the pitch of mini-LEDs. To mount mini-LEDs and control ICs at the same time needs the technical innovations because they have different surface finishes. Moreover, there is no solder resist layer on a substrate because of the fine-pitch of mini-LEDs and control ICs in a single pixel. The Solder-on-Pad (SoP), fluxing underfill, and Laser-Assisted Bonding (LAB) technologies are developed to implement digital signage modules, successfully.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"1031-1036"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88136197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations","authors":"Ankit Kaul, Sreejith Kochupurackal Rajan, Md Obaidul Hossen, G. May, M. Bakir","doi":"10.1109/ectc32862.2020.00231","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00231","url":null,"abstract":"In this paper, a BEOL-embedded chiplet integration scheme is proposed for dense 3D integration. This scheme represents a system with multiple device tiers (primary and embedded tiers) where custom chiplets, such as voltage regulator modules, I/O drivers, RF front-end chips, etc. are embedded into the BEOL of an application processor tier with a monolithic memory device tier, such as resistive RAM. The proposed integration scheme is thermally evaluated to investigate the effects of design parameters on the thermal operation of the primary and embedded tiers, along with transient analysis to estimate the extent of inter-tier thermal coupling. Results for steady-state operation suggest the thermal viability of such an integration approach. Considerable reduction in inter-tier thermal coupling for transient operation was achieved with dual-sided cooling (tier 1 to tier 3 coupling: 85% for air-cooling, reduced to 65% for dual-sided cooling). We also propose and demonstrate metal electroless plating in addition to mechanical self-alignment as an enabling technology for BEOL-embedded integration to facilitate low-temperature, low-pressure, and high interconnect density inter-die bonding. Post assembly Ni electroless deposited bonding was verified across all inspected diagonal pillars in an area array of 50×50 copper pillars.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"83 1","pages":"1459-1467"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85895025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Best Paper Awards from the Previous ECTC Held in 2019","authors":"","doi":"10.1109/ectc32862.2020.00010","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00010","url":null,"abstract":"","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86314088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of the Mechanical Behavior of SAC305 Solder Joints at Extreme High Temperatures Using Nanoindentation","authors":"M. Alam, KM Rafidh Hassan, Abdullah Fahim, Jing Wu, Sudan Ahmed, J. Suhling, P. Lall","doi":"10.1109/ectc32862.2020.00338","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00338","url":null,"abstract":"Solder joints provide mechanical support, and electrical and thermal interconnection between packaging levels in microelectronics assemblies. Proper functioning of these interconnections and the reliability of the electronic packages depend largely on the mechanical properties of the solder joints. Lead free solders typically provide excellent thermo-mechanical properties and are commonly used as interconnections in electronic packages. However, the exposure of lead free solder joints to complicated thermal histories can degrade their mechanical behavior. For example, aging of lead free solders at high temperature leads to microstructural evolution resulting in reduced mechanical properties and increased creep deformations. Previous investigations on mechanical characterization of lead free solders have mainly emphasized mechanical testing at temperatures up to 125 °C. However, many electronic products are deployed in harsh environment applications including well drilling, geothermal energy, automotive power electronics, and aerospace engines, where solders are exposed to very high temperatures from 125-200 °C. Mechanical properties of lead free solders at elevated temperatures are limited.In this work, we have explored Mechanical behavior and aging effects in SAC305 (96.5Sn-3.0Ag-0.5Cu) solder joints at several extreme high testing temperatures (T = 125, 150, 175, and 200 °C) using the method of nanoindentation. A special high temperature stage and test protocols were used within the nanoindentation system to carefully control the testing temperature, and to make the measurements insensitive to thermal drift problems. Solder joints were extracted from 14 x 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that were built as part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project. Since the properties of SAC solder joints are highly dependent on crystal orientation, polarized light microscopy was utilized to determine the orientation of the tested joints. For all the experiments, only single grain solder joints were used to avoid introducing any unintentional variation from changes in the crystal orientation across the joint cross-section.To study aging effects, solder joints were preconditioned for 0, 1, 5, 10, and 30 days at T = 125 °C in a box oven. Nanoindentation testing was then performed on the aged specimens at four different test temperatures (T = 125, 150, 175, and 200 °C) to extract the elastic modulus, hardness, and creep performance of the aged material. Throughout this study, a constant force of 10 mN was applied for 900 seconds to monitor the creep displacements and measure the creep strain rate as a function of both temperature and prior aging conditions.As expected, our results have shown that mechanical properties and creep strain rate of solder joints are highly dependent on the test temperature and degrade significantly as the temperature increases. In particular, the aging induced degradation r","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2175-2184"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89142630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Investigation of Ultra Fine Line, Multi-Layer Copper Routing for Fan-Out Packaging Using a Newly Designed Micro Tensile Test Method","authors":"M. Woehrmann, Aleksander Keller, T. Fritzsch, M. Schiffer, A. Gollhardt, H. Walter, M. Schneider-Ramelow, K. Lang","doi":"10.1109/ectc32862.2020.00146","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00146","url":null,"abstract":"Fan-Out enables new heterogeneous packaging concepts where chips are embedded in an electronic mold compound (EMC) package with ultra-small footprint. These multi-chip systems demand a high routing density in the redistribution layer (RDL) which is realized by fine copper features with line and space structures in the dimension down to 2 μm, establishing electrical interconnects between the chips across different substrate materials (e.g. silicon chips and mold-filled gaps). The copper lines undergo high mechanical stress due different thermal expansion coefficients of the used materials. Numerous papers investigated reliability topics only focusing on properties of the polymer in the redistribution layer and the solder ball material, but the influence of the mechanical properties of electroplated copper has been a minor topic so far [1] [2] [3].With feature sizes and thicknesses of about 2 μm, these structures are in the range of copper grain size with the result that different grain structures become more important. Also, the material suppliers start to tune galvanic copper baths to generate e.g. twinned copper structures with mechanically superior behavior. Characterizing these fine structures at that scale is challenging because the properties could be different compared to macro samples. This work presents an on-wafer characterization method of copper features down to 2 μm with a newly designed wafer scale micro tensile test. This concept allows a test integration in the fab process flow. The elongation at break and the tensile strength of ultra fine line copper lines are measured by the tensile loading. The results are compared with macro scale tensile tests.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"893-899"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83629595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging","authors":"Prayudi Lianto, Chin Wei Ronnie Tan, Qi Jie Peng, Abdul Hakim Jumat, Xundong Dai, Khai Mum Peter Fung, Guan Huei See, S. Chong, Soon Wee David Ho, Siew Boon Serine Soh, Seow Huang Sharon Lim, Hung Ming Calvin Chua, Ahmad Abdillah Haron, Huan Ching Kenneth Lee, Mingsheng Zhang, Zhi Hao Ko, Ye Ko San, Henry Leong","doi":"10.1109/ectc32862.2020.00181","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00181","url":null,"abstract":"Fan-Out wafer-level packaging (FOWLP) semi-additive process (SAP) flow for three layers of redistribution layer (RDL) has been developed. Patched dicing lane design is adopted to improve RDL plating uniformity by ~40x, as measured by sheet resistance (Rs). We demonstrate warpage correction solution to improve pattern integrity despite tool handling limitations. We also demonstrate a CMP solution to improve 2/2um L/S RDL pattern integrity by >10x. We achieve RDL mechanical integrity through an integrated endpoint-detection-controlled wet etch solution to achieve <50nm undercut and extend SAP process to sub-2/2um L/S RDL. We also establish RDL electrical integrity by integrating wafer treatment solution after RDL formation to achieve line-to-line leakage current <0.1nA. Upon completion of wafer-level process, package assembly is carried out using SAC305 BGA onto PCB. Package integrity is examined using X-ray, followed by a progressive thermal cycling (TC) reliability test. RDL mechanical and electrical integrity is proven from the board-level reliability test where the RDL layers pass 1000 TC and failure occurs on the BGA level.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"45 1","pages":"1126-1131"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80010246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}