2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding","authors":"Soon-Wook Kim, F. Fodor, N. Heylen, S. Iacovo, J. de Vos, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/ectc32862.2020.00046","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00046","url":null,"abstract":"This paper presents our approach to hybrid bond scaling to 1μm pitch and recent demonstration results. The direct wafer stacking of two Cu/SiCN surface is realized between slightly protruding Cu nano-pad on one wafer and slightly recessed, but larger, Cu nano-pad on the second wafer. The protruding nano-pad is tailored as smaller than the recessed nano-pad to compensate for the overlay tolerance in the wafer-to-wafer (W2W) bonding. To control the stability and performance of Cu nano-pad integration process, the intensive inline atomic force microscopy (AFM) and surface acoustic microscopy (SAM) characterization is used on various test structures before/after wafer bonding. The surface flatness should be less than 1 nm/μm to ensure void free bonding. This surface planarization is readily achieved for Cu pad densities up to 25%. Finally, we have demonstrated the high yield and low resistance performance across the 300mm wafer for hybrid bond pitches between 5 and 1μm.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":"216-222"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85452885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Semi-Hemispherical High Q-Factor Resonators Fabricated using a Hybrid Rigid-Flex Process","authors":"Vincens Gjokaj, P. Chahal","doi":"10.1109/ECTC32862.2020.00356","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00356","url":null,"abstract":"In this paper, a 3D printed high-Q semihemispherical resonator fed by a coax-like transmission line is demonstrated. The semi hemispherical resonator was fabricated using polyjet printing followed by blanket metalization. It is coupled to a two-part coax-like transmission line using a slot in the 3D printed structure. The coax-like structure is fabricated using a hybrid process, combining 3D printing and fine line patterning using microlithography. Unloaded Q-factor of >8000 is measured near 44 GHz. This work shows that a 3D printed high-Q resonator can readily be coupled with microfabricated circuits on a printed circuit board or a flex substrate. Details of design, fabrication, and measurements are presented, and the measured and simulation results match closely.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"126 1","pages":"2284-2288"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85506557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guided-mode Resonance Filter for Micro-optic Spectrometer","authors":"J. Inoue, S. Ura, K. Kintaka","doi":"10.1109/ectc32862.2020.00283","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00283","url":null,"abstract":"Spectrometers are usually composed of diffraction gratings and prisms, and become large in size for high wavelength resolution. High-density integration of narrowband-pass filters of different wavelengths on a substrate can be expected to produce an ultra-compact spectrometer. We focused on guided-mode resonance (GMR) filters as such filters. The GMR filter consists of a thin-film waveguide and a sub-wavelength grating. GMR filters of different filtering wavelengths can be integrated in the same substrate because their periodic structure in refractive index spread along in-plane direction. On the other hand, GMR filter normally needs an aperture size and beam diameter of hundreds of microns and is not suitable for high-density integration. In this study, we proposed and investigated a GMR filter of a single-layer cross grating for a compact narrowband-pass filter. Different guided modes contributing to the broadband and narrowband reflection propagate orthogonally each other. By using simultaneously these guided modes, both reflections are cancelled at the competing wavelengths, resulting in high transmittance. In this paper, design examples with numerical simulation results are presented. It was predicted that a passband of 15 nm was obtained in the stopband of 200 nm for an incident beam of a 10-micron diameter.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"1812-1817"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80189654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct Printing of Antennas on Large 3D Printed Plastic Structures","authors":"Vincens Gjokaj, C. Crump, Brian Wright, P. Chahal","doi":"10.1109/ectc32862.2020.00110","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00110","url":null,"abstract":"A new method of integrating passive components on large non-planar parts (example, automotive bumpers) using conductive spray inks and a shadow mask coupled with a damascene-like process is presented. The sprayed conductive ink acts as a catalyst for electro- or electroless-plating of copper. Structures with fine resolution can readily be printed using this process. A Vivaldi antenna operating in the V-band is demonstrated on a 3D printed scaled down automotive bumper. The proposed method is simple, reduces waste, and can readily be adopted in the integration of passive components on large plastic structures, especially for automotive applications. Details of design, fabrication, and measurement are presented.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"666-670"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80251780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Autocatalytic tin - how to overcome process limitations to introduce a new solution for thick tin plating","authors":"K. Johal, B. Schafsteller, G. Ramos, K. Tuna, S. Nelle","doi":"10.1109/ectc32862.2020.00308","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00308","url":null,"abstract":"The autocatalytic deposition of tin is gaining increasing interest as it offers several benefits compared to the immersion type deposition. Despite the fact that in contrast to the immersion plating process there is no technical limitation of the thickness of the tin deposit, it also allows the deposition of tin on different materials other than copper. With this, it can open up new application fields for plating deposits, which are not considered for electroless plating yet.Even though there is a great potential for this technology, there are limitations that have prevented the successful introduction of this process so far. One limitation of possible electrolyte formulations is for example, that the plating rate of the process is instable as it tends to drop already after few minutes of dwell time. One target of the investigations presented in this paper was to understand the root cause of this deposition rate drop. In order to clarify the reaction mechanisms different electrochemical approaches were used to determine the chemical background. It could be proven, that the Pyrophosphate which is used as complexing agent in many autocatalytic tin solutions [1], [2], [3], [4] adsorbs to the electrode surface and that due to that adsorption, the plating reaction of tin is inhibited.Based on this finding a bath formulation was created, which is able to overcome this inhibiting effect and providing a stable plating performance over the entire bathlife.In this paper exemplary tin deposits are presented which were plated with an autocatalytic electrolyte comparing their layer properties to those of other conventional final finishes like immersion tin or electroless nickel/immersion gold. To judge the performance of the final finish, solder wetting behavior and solder joint reliability were rated and compared. It is also shown, that the electrolyte solution can be tailored in composition and plating parameters to fulfill requirements such as defined layer roughness or the capability for plating of fine patterns.The presented results will allow to consider the autocatalytic tin deposition as a potential solution for specific applications in e.g. the IC substrate and µ-LED market.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"1979-1985"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80582703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Packaging and System-Integration Platform with Integrated Antennas for Scalable, Low-Cost and High-Performance 5G mmWave Systems","authors":"I. Ndip, K. Andersson, Stefan Kosmider, T. H. Le, A. Kanitkar, M. van Dijk, Kavin Senthil Murugesan, U. Maass, T. Löher, Marco Rossi, J. Jaeschke, A. Ostmann, R. Aschenbrenner, M. Schneider-Ramelow, K. Lang","doi":"10.1109/ectc32862.2020.00029","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00029","url":null,"abstract":"In this work, we present a novel packaging and system-integration platform with integrated antennas (antenna-in-package, AiP, platform) for 5G millimeter-wave (mmWave) systems. We illustrate the application of the platform for the development of miniaturized, scalable, low-cost and high-performance 5G mmWave systems for new radio (NR) base stations. RF characterization of the dielectric material of the platform and the integrated mmWave antennas as well as thermal investigations of the platform are presented. The process steps required for the fabrication of the platform are discussed, and an example of a mmWave chip embedded in the platform is shown.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"101-107"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80469461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Direct Multi-Field Coupling Methodology for Modeling Moisture-Induced Stresses and Delamination in Electronic Packages","authors":"Liangbiao Chen, Xuejun Fan, Yong Liu","doi":"10.1109/ectc32862.2020.00172","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00172","url":null,"abstract":"A direct multi-field coupling method is proposed to integrate hygroscopic swelling and vapor pressure effects with thermos-mechanical stress. Moisture diffusion is modeled using water activity theory that is a unified and versatile approach for multi-materials systems. Water activity theory can be simply understood as an alternative normalization approach with normalized concentration defined as ${overline C _k} = {a_w} = C/K$, where K is the generalized solubility. Vapor pressure pw is calculated as pw = psat • aw according to water activity definition (i.e., water activity is the ratio between the vapor pressure and saturated vapor pressure psat). The integration of water vapor pressure is achieved by the effective stress theory assuming polymeric materials as porous medium with vapor pressure acting on the skeletal portion. An equivalent coefficient of diffusion expansion (CDE) is derived as a new material property to consider both the hygroscopic swelling and vapor pressure effects. For isotropic materials, CDE can be expressed as CDE=CHS+pSat(/(3B • K), where CHS is the coefficient of hygroscopic swelling and B is bulk modulus. It can be seen from the equation that vapor pressure effects can be significant at high temperatures when the saturated vapor pressure is high but material modulus is low. The equivalent CDE method is applied to study the delamination of solder mask in a low-profiled ball grid array (LPBGA) package subjected to moisture preconditioning and reflow process. The direct coupling of thermal stresses and moisture-induced stresses is performed in ANSYS using its coupled-field elements. The results of the simulation match well with the experimental observations. The design of experiments shows that increasing the solder mask thickness could reduce solder mask tensile stress/strain and thus provides a viable solution to reduce the delamination issues.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"62 1","pages":"1064-1069"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80657842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Pen-Writable Electroless Plating Method for Large-Area RF Circuit Applications","authors":"Yihang Chu, P. Chahal","doi":"10.1109/ECTC32862.2020.00275","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00275","url":null,"abstract":"This paper proposes a novel, large area, low temperature compatible approach to the fabrication of RF electronics through a combination of AM methods and electroless plating. A silver nanoparticle based ink containing particles averaging ~35 nm in size was loaded into ballpoint pens which were used to directly write 868 MHz RFID antennas upon a waterproof inkjet positive film with a microporous coating. After curing, the components were subjected to Cu electroless plating to increase conductivity, resulting in fully functional, flexible and water-resistant devices demonstrating read ranges up to 0.85 m. The effects of the Cu electroplating upon the morphology of the conductive surface and RFID antenna performance were examined. It was found that the addition of the electroless plating provided a notable enhancement to device performance without significantly impacting the advantages of high-throughput, simplicity and low cost offered by AM methods.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1763-1768"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83069589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Progress and Applications of Embedded System in Chip (eSinC®) Technology","authors":"Shuying Ma, Jia-Hwang Chang, Jiao Wang, Daquan Yu, A. Xiao, Xiaobing Yang, Tony Curtis","doi":"10.1109/ECTC32862.2020.00262","DOIUrl":"https://doi.org/10.1109/ECTC32862.2020.00262","url":null,"abstract":"With the rise of artificial intelligence, automatic driving, 5G, Internet of things and other emerging industries, the demand of 3D integrated packaging technology is increasing strongly to meet the ever-increasing market demands of high performance, small size, high reliability and ultra-low power consumption. This paper presents a new 3D system integrated packaging technology named embedded system in chip (eSinC®) technology. This technology is a combination of TSV technology and eSiFO technology which has been reported in 2016 [1]-[4]. After finishing the standard eSiFO process, backside RDLs and via last TSV process were fabricated by using laser temporary bonding technology. A totally three stacking package including five chips with two layer frontside and backside RDLs was fabricated successfully. Individual package was connected by micro bumps and TSVs. The packaging size is 5×5mm with an overall 0.78mm packaging thickness, while the individual eSinC packaging thickness is 0.28mm. Several key technologies were developed to achieve eSinC package, including high aspect ratio TSVs, wafer thin and handling, low temperature PECVD process, as well as temporary bonding. Good electrical yield was achieved after process optimization.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"81 1","pages":"1671-1676"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82849865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromigration Failure Study of a Fine-pitch 2μm/2μm L/S Cu Redistribution Line Embedded in Polyimide for Advanced High-density Fan-out Packaging","authors":"Chien-Lung Liang, Yung-Sheng Lin, C. Kao, D. Tarng, Shan-Bo Wang, Y. Hung, Kwang-Lung Lin","doi":"10.1109/ectc32862.2020.00065","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00065","url":null,"abstract":"The Cu redistribution line (RDL) in advanced fan-out (FO) packages is approaching 1-2 µm or even a submicron-scale feature size for achieving high-density (input/output (I/O) number > 1000) packaging requirements. The downsizing trend of the Cu RDL gives rise to an increasing current density which will be greater than 105 A/cm2 in a 2µm/2µm line/space (L/S) trace. The electromigration reliability concerns caused by the electrical-thermal coupling effects may be raised accordingly. The present study reported the electromigration failure behavior and mechanism of a fine-pitch 2μm/2μm L/S Cu RDL, 20 μm in length and 3 μm in thickness, embedded in polyimide (PI) dielectric layer for advanced high-density FO packaging. The Cu RDL was stressed with a direct current with 53 mA (8.8 × 105 A/cm2) at 180°C in accordance with the JEDEC standard. After the thermal annealing pre-treatment at 230°C for 6 h, a porous Cu oxide layer accompanying a few nanovoids was formed on top of the Cu RDL. The electromigration test was found to accelerate the oxidation behavior and voiding issue with increasing current stressing time. A bilayer Cu oxide structure was formed upon electromigration, while the nanovoids formed at the oxide/RDL interface increased in number and enlarged in dimension. Large voids formed underneath the Cu RDL, at the Cu RDL/Ti adhesion layer interface, were also observed. These phenomena were responsible for the steady resistance increase under the electromigration test. Once the Cu RDL has been occupied with voids formed upon electromigration, the rapid reduction in the cross-sectional area will give rise to current crowding and thus induce an increasing RDL temperature. The abruptly rising temperature caused the local melting of the Cu RDL and disruption of the neighboring multilayers. The open circuit failure that occurred in the middle region of the Cu RDL, whereas not in the cathode region, suggests a prominent thermal effect induced failure mechanism under the electromigration test.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"361-366"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90865922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}