2020 IEEE 70th Electronic Components and Technology Conference (ECTC)最新文献_第4页

Design and Fabrication of Band-Pass Filter on Glass IPD for 5G New Radio 5G新型无线电玻璃IPD带通滤波器的设计与制造

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00277

Pao-Nan Lee, Yu-Chang Hsieh, Sheng-Chi Hsieh, C. Kung, Chen-Chao Wang

引用次数: 8

Planar-Radial Structured Thermoelectric Cooler for Local Hot Spot Cooling in Mobile Electronics 用于移动电子器件局部热点冷却的平面-径向结构热电冷却器

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00349

C. Kim, Min-Woo Jeong, Sungtae Kim, Seung-Hyun Oh, So-Yeon Lee, Young-Chang Joo, Haishan Shen, Hoojeong Lee, Jeonglim Yoon, Youngcheol Joo

{"title":"Planar-Radial Structured Thermoelectric Cooler for Local Hot Spot Cooling in Mobile Electronics","authors":"C. Kim, Min-Woo Jeong, Sungtae Kim, Seung-Hyun Oh, So-Yeon Lee, Young-Chang Joo, Haishan Shen, Hoojeong Lee, Jeonglim Yoon, Youngcheol Joo","doi":"10.1109/ectc32862.2020.00349","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00349","url":null,"abstract":"In recent years, clock speed and power density have increased rapidly, improving the performance of mobile devices, and thus, thermal management issues for local hot spots of chips are increasing. Dynamic thermal management (DTM) through frequency modulation and passive cooling components such as heat pipes is currently being used as a cooling strategy for mobile devices. However, DTM has an inverse relationship with chip performance, and passive cooler occupy too much space for local hot spot cooling. From the point of view of local hot spot cooling, a solid-state thermoelectric cooler (TEC) has the advantage of enabling on/off control and site-specific cooling. However, most of the research on TECs focuses on the material or interfacial properties of TECs, not the design rule or structure of TECs for practical applications. This study proposes an active cooling device using a TEC with a unique planar-radial structure that can selectively cool only locally generated hot spots and minimize form factor designs with 2D structures, making this cooling device highly applicable to mobile devices. A 5-pair TEC using the optimized TE leg thickness (n-Bi2Te3 5.05 μm and p-Sb2Te3 5.45 μm) and radial structure enhanced the Peltier effect and confirmed the maximum junction temperature difference of 2.4 °C. By adopting a hybrid cooling system combining active and passive coolers in a mobile device, we obtained an effective cooling area ratio of 4 and a cooling effect (~3.87 °C).","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"2242-2246"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90453459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Role of Grain Size on the Effective Resistivity of Cu-Graphene Hybrid Interconnects 晶粒尺寸对cu -石墨烯杂化互连有效电阻率的影响

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00254

Rahul Kumar, Sunil Pathania, Surila Guglani, Ajay Kumar, Somesh Kumar, Sourajeet Roy, B. Kaushik, Rohit Sharma

{"title":"Role of Grain Size on the Effective Resistivity of Cu-Graphene Hybrid Interconnects","authors":"Rahul Kumar, Sunil Pathania, Surila Guglani, Ajay Kumar, Somesh Kumar, Sourajeet Roy, B. Kaushik, Rohit Sharma","doi":"10.1109/ectc32862.2020.00254","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00254","url":null,"abstract":"At sub-22nm technology nodes, size effects play a prominent role in the performance degradation of Cu interconnects. Several scattering mechanisms contribute to size effects, including surface roughness and grain boundary scattering as grain sizes in Cu decreases with reduced line widths. Due to these scattering phenomena, the resistivity of Cu interconnects increases drastically, which leads to electrical and thermal performance degradation and reliability issues. To address these limitations, researchers have proposed Cu- Graphene hybrid interconnects, where the line resistance due to Cu and Graphene is connected in parallel leading to smaller effective resistances. In this paper, we present analytical models of the reduction in effective resistivity obtained due to enlargement of grain size. The reduction in effective resistivity is due to the hybrid interconnect geometry and grain size enlargement. We present a qualitative analysis for the resistivity, mean free path, delay and energy delay product of the three interconnect technology nodes from 22nm to 7nm Cu widths. Our analysis shows that Cu on-chip interconnects with Graphene as a barrier layers shows 47%, 30% and 19% improvement in resistivity, delay and energy delay product respectively due to grain size enlargement at 13nm technology node.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"1620-1625"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89228501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Large-body-sized Glass-based Active Interposer for High-Performance Computing 用于高性能计算的大尺寸基于玻璃的有源中介器

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00144

Siddharth Ravichandran, M. Kathaperumal, M. Swaminathan, R. Tummala

{"title":"Large-body-sized Glass-based Active Interposer for High-Performance Computing","authors":"Siddharth Ravichandran, M. Kathaperumal, M. Swaminathan, R. Tummala","doi":"10.1109/ectc32862.2020.00144","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00144","url":null,"abstract":"This paper presents a next generation glass-based active interposer with 2 micron polymer RDL. Passive 2.5D interposers have become a mainstream solution to address the bandwidth demands of high-performance computing (HPC) applications. However, such passive interposers face challenges in meeting future performance, cost and reliability needs and active interposers have been studied recently as a means of scaling interposer performance. Given the ability to grow CMOS on Silicon more readily, only Silicon has been studied as substrate core for active interposers. However, for large body sizes, Silicon is not cost effective and interconnects tend to be lossy over long distances. Glass has been explored as a passive interposer core previously, and glass-based panel embedding (GPE) solutions have also been developed for fanout applications. This work uses GPE technology to demonstrate a glass-based active interposer substrate with potential for large-body-sized packages. The key challenge, however, in achieving a wiring density of over 250 IO/mm is the surface non-coplanarities associated with cavities in glass substrates. This paper describes the fabrication process for a Glass-based active interposer with dies embedded in glass cavities, and a systematic parametric process optimization to improve the surface planarity to demonstrate 2 micron L/S RDL on die-embedded glass substrates.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"879-884"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76779936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Effect of Ni(P) thickness of ultrathin ENEPIG on the interfacial reaction and board level reliability of solder joints 超薄ENEPIG中Ni(P)厚度对焊点界面反应及板级可靠性的影响

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00114

Yibo Wang, H. Pan, Chen Chen, Ming Li, Liming Gao

{"title":"Effect of Ni(P) thickness of ultrathin ENEPIG on the interfacial reaction and board level reliability of solder joints","authors":"Yibo Wang, H. Pan, Chen Chen, Ming Li, Liming Gao","doi":"10.1109/ectc32862.2020.00114","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00114","url":null,"abstract":"The amorphous Ni(P) layer in traditional Electroless Ni/Electroless Pd/Immersion Au (ENEPIG) surface finish has an adverse effect on its performance in high speed circuits due to the relatively high electrical resistance which will cause impact to the signal integrity. By limiting the thickness of Ni(P)layerless than 1μm in ultrathin ENEPIG, the impedance can be significantly reduced and its solderability and corrosion resistance remain as good as those of traditional ENEPIG. In this article, two kinds of ultrathin ENEPIG with Ni(P) layer thicknesses of 0.112 and 0.185μm respectively were reflowed with commercial Sn-3.0Ag-0.5Cu solder. After that the morphology and growth of interfacial IMC were investigated using SEM and EDS analysis. Solder ball shear test, drop test and thermal cycle test (TCT) were then conducted to evaluate their bonding strength as well as performance in board level reliability tests. Results showed that although Ni(P) layer was depleted soon in ultrathin ENEPIG samples, the Ni-Sn-P layer could still act as a diffusion barrier and hinder the growth of brittle IMC, which contributed a lot to the bonding strength. Ultrathin ENEPIG samples with 0.185μm Ni(P) layer survived both TCT and drop test and showed better reliability than electroplated Ni/Au in drop test and better resistance to thermal fatigue than OSP in TCT, indicating that ultrathin ENEPIG could satisfy the reliability requirement for actual application.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"316 1","pages":"690-695"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75548078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ECTC 2020 Breaker Page ECTC 2020断路器页

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00003

引用次数: 0

Synthesis of Boron Nitride Coated Silica Filler for Preparing Thermally Conductive Epoxy Composites 制备导热环氧复合材料用氮化硼包覆二氧化硅填料的合成

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00314

Jiaxiong Li, Yanjuan Ren, D. An, K. Moon, C. Wong

{"title":"Synthesis of Boron Nitride Coated Silica Filler for Preparing Thermally Conductive Epoxy Composites","authors":"Jiaxiong Li, Yanjuan Ren, D. An, K. Moon, C. Wong","doi":"10.1109/ectc32862.2020.00314","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00314","url":null,"abstract":"Increasing power density in the modern electronics with continuous miniaturization and rapid growth in functionality demands fast heat removal capability of the package from the chip. Traditional encapsulant materials such as epoxy molding compounds or underfills are seen as poor thermal conductor due to the low intrinsic thermal conductivity of the fused silica fillers (~1 W/mK) extensively used in formulating these epoxy encapsulants. Boron nitride (BN) possesses extraordinarily high thermal conductivity (~400 W/mK in plane) but its 2-D platelet shape limits the loading level due to the rheological issues. In this work, the BN coated silica (BN@SiO2) fillers are synthesized through silane assisted assembly method. The chemical modification on the filler interface chemistry and the morphology of the synthesized BN@SiO2 is discussed in detail. A significantly reduced viscosity at various shear rates demonstrates the better flowability of epoxy loaded with BN@SiO2 fillers compared to those directly mixed with BN and SiO2 fillers, indicating the potential of further increase of BN loading level. Moreover, the much-improved thermal conductivity in these composites (~0.7 W/mK at 30 wt% loading) suggests that the as synthesized BN@SiO2 could be promising candidate to prepare highly thermally conductive epoxy encapsulants in order to effectively dissipate the heat generated from high performance chips.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"2019-2024"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73139571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermal aging reliability of socketable, surface-modified solder BGAs with and without polymer collars 带或不带聚合物环的嵌套式、表面改性焊料BGAs的热老化可靠性

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00087

Omkar Gupte, G. Murtagian, R. Tummala, V. Smet

{"title":"Thermal aging reliability of socketable, surface-modified solder BGAs with and without polymer collars","authors":"Omkar Gupte, G. Murtagian, R. Tummala, V. Smet","doi":"10.1109/ectc32862.2020.00087","DOIUrl":"https://doi.org/10.1109/ectc32862.2020.00087","url":null,"abstract":"Ball Grid Array (BGA) package designs are increasingly used in surface mount applications while Land Grid Array (LGA) designs are predominantly used in socketing. The need to converge to a single package design has been driving the need to enable socketable BGAs. BGA spheres with a noble metal surface provide a stable mechanical contact interface with the socket paddles. These noble contact interfaces, however, have to remain intact through the socketing life of the product, considering accelerated testing temperatures of 100-120 °C. Under such conditions, it has been reported that the solder from the ball-attach joints undergoes solid-state wicking along the surface of the ball, leading to complete Au dissolution and potential undesirable intermetallic formation with the socket paddles, along with a drop in ball shear strength due to depletion of the solder from the joints. This paper discusses the use of polymer collars to address this challenge and improve the thermal aging reliability of packages with surface-modified BGA interconnections. The polymer collars were spin-coated on the package, which was aged alongside a reference package with no collars, at accelerated test temperatures of 100 °C and 120 °C, respectively. XPS studies showed that after 650 h of aging, no Au signal but a strong Sn signal was observed in the package without collars, which confirmed complete solder wicking to the top of the ball, while the Au signal remained for the package with the collars, confirming that polymer collars are effective in inhibiting solid-state solder wicking from the ball-attach joints. The joints with polymer collars also showed mechanical stability throughout thermal aging with a 3X improvement in joint shear strength.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"512-517"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72705381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An Efficient and Fast 112Gbps/PAM4 Signal Line Design with Conventional FCBGA Substrate Based on a 3-D Component Library 基于三维元件库的传统FCBGA衬底高效快速112Gbps/PAM4信号线设计

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00156

R. Oikawa

引用次数: 0

3D Heterogeneous and Flexible Package Integration for Zero-Power Wireless Neural Recording 零功率无线神经记录的三维异构和柔性封装集成

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Pub Date : 2020-06-01 DOI: 10.1109/ectc32862.2020.00163

S. Y. B. Sayeed, S. B. Venkatakrishnan, M. Monshi, Abdal Abdulhameed, J. Volakis, P. Raj

引用次数: 0