Large-body-sized Glass-based Active Interposer for High-Performance Computing

Siddharth Ravichandran, M. Kathaperumal, M. Swaminathan, R. Tummala
{"title":"Large-body-sized Glass-based Active Interposer for High-Performance Computing","authors":"Siddharth Ravichandran, M. Kathaperumal, M. Swaminathan, R. Tummala","doi":"10.1109/ectc32862.2020.00144","DOIUrl":null,"url":null,"abstract":"This paper presents a next generation glass-based active interposer with 2 micron polymer RDL. Passive 2.5D interposers have become a mainstream solution to address the bandwidth demands of high-performance computing (HPC) applications. However, such passive interposers face challenges in meeting future performance, cost and reliability needs and active interposers have been studied recently as a means of scaling interposer performance. Given the ability to grow CMOS on Silicon more readily, only Silicon has been studied as substrate core for active interposers. However, for large body sizes, Silicon is not cost effective and interconnects tend to be lossy over long distances. Glass has been explored as a passive interposer core previously, and glass-based panel embedding (GPE) solutions have also been developed for fanout applications. This work uses GPE technology to demonstrate a glass-based active interposer substrate with potential for large-body-sized packages. The key challenge, however, in achieving a wiring density of over 250 IO/mm is the surface non-coplanarities associated with cavities in glass substrates. This paper describes the fabrication process for a Glass-based active interposer with dies embedded in glass cavities, and a systematic parametric process optimization to improve the surface planarity to demonstrate 2 micron L/S RDL on die-embedded glass substrates.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"879-884"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ectc32862.2020.00144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

Abstract

This paper presents a next generation glass-based active interposer with 2 micron polymer RDL. Passive 2.5D interposers have become a mainstream solution to address the bandwidth demands of high-performance computing (HPC) applications. However, such passive interposers face challenges in meeting future performance, cost and reliability needs and active interposers have been studied recently as a means of scaling interposer performance. Given the ability to grow CMOS on Silicon more readily, only Silicon has been studied as substrate core for active interposers. However, for large body sizes, Silicon is not cost effective and interconnects tend to be lossy over long distances. Glass has been explored as a passive interposer core previously, and glass-based panel embedding (GPE) solutions have also been developed for fanout applications. This work uses GPE technology to demonstrate a glass-based active interposer substrate with potential for large-body-sized packages. The key challenge, however, in achieving a wiring density of over 250 IO/mm is the surface non-coplanarities associated with cavities in glass substrates. This paper describes the fabrication process for a Glass-based active interposer with dies embedded in glass cavities, and a systematic parametric process optimization to improve the surface planarity to demonstrate 2 micron L/S RDL on die-embedded glass substrates.
用于高性能计算的大尺寸基于玻璃的有源中介器
提出了一种2微米聚合物RDL的新一代玻璃基活性中间体。无源2.5D中介器已经成为解决高性能计算(HPC)应用带宽需求的主流解决方案。然而,这种被动中介器在满足未来性能、成本和可靠性需求方面面临挑战,而主动中介器最近被研究为扩展中介器性能的一种手段。考虑到在硅上更容易生长CMOS的能力,只有硅被研究作为有源中间体的衬底核心。然而,对于大尺寸的机身来说,硅并不具有成本效益,并且在长距离上互连往往会损耗。玻璃已经被探索作为被动中间层核心,玻璃基面板嵌入(GPE)解决方案也被开发用于扇出应用。这项工作使用GPE技术展示了一种基于玻璃的有源中间体基板,具有大尺寸封装的潜力。然而,实现超过250 IO/mm的布线密度的关键挑战是与玻璃基板中的空腔相关的表面非共面性。本文介绍了一种玻璃基有源中间体的制造工艺,并对其进行了系统的参数化工艺优化,以提高表面平面度,从而在玻璃基板上实现2微米L/S RDL。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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