Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

Soon-Wook Kim, F. Fodor, N. Heylen, S. Iacovo, J. de Vos, Andy Miller, G. Beyer, E. Beyne
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引用次数: 31

Abstract

This paper presents our approach to hybrid bond scaling to 1μm pitch and recent demonstration results. The direct wafer stacking of two Cu/SiCN surface is realized between slightly protruding Cu nano-pad on one wafer and slightly recessed, but larger, Cu nano-pad on the second wafer. The protruding nano-pad is tailored as smaller than the recessed nano-pad to compensate for the overlay tolerance in the wafer-to-wafer (W2W) bonding. To control the stability and performance of Cu nano-pad integration process, the intensive inline atomic force microscopy (AFM) and surface acoustic microscopy (SAM) characterization is used on various test structures before/after wafer bonding. The surface flatness should be less than 1 nm/μm to ensure void free bonding. This surface planarization is readily achieved for Cu pad densities up to 25%. Finally, we have demonstrated the high yield and low resistance performance across the 300mm wafer for hybrid bond pitches between 5 and 1μm.
1 μm间距杂化晶圆键合的Cu/SiCN表面形貌控制
本文介绍了我们将杂化键缩放到1μm间距的方法和最近的演示结果。两个Cu/SiCN表面的直接晶圆堆叠是在一个晶圆上微凸的Cu纳米片和另一个晶圆上微凹但较大的Cu纳米片之间实现的。凸出的纳米衬垫比凹进的纳米衬垫更小,以补偿晶圆到晶圆(W2W)键合中的覆盖公差。为了控制铜纳米焊片集成过程的稳定性和性能,采用密集的在线原子力显微镜(AFM)和表面声学显微镜(SAM)对晶圆键合前后的各种测试结构进行了表征。表面平整度应小于1 nm/μm,以保证无空隙粘接。当铜垫密度达到25%时,这种表面平面化很容易实现。最后,我们展示了在5到1μm之间的杂化键间距在300mm晶圆上的高良率和低电阻性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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