BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations

In this paper, a BEOL-embedded chiplet integration scheme is proposed for dense 3D integration. This scheme represents a system with multiple device tiers (primary and embedded tiers) where custom chiplets, such as voltage regulator modules, I/O drivers, RF front-end chips, etc. are embedded into the BEOL of an application processor tier with a monolithic memory device tier, such as resistive RAM. The proposed integration scheme is thermally evaluated to investigate the effects of design parameters on the thermal operation of the primary and embedded tiers, along with transient analysis to estimate the extent of inter-tier thermal coupling. Results for steady-state operation suggest the thermal viability of such an integration approach. Considerable reduction in inter-tier thermal coupling for transient operation was achieved with dual-sided cooling (tier 1 to tier 3 coupling: 85% for air-cooling, reduced to 65% for dual-sided cooling). We also propose and demonstrate metal electroless plating in addition to mechanical self-alignment as an enabling technology for BEOL-embedded integration to facilitate low-temperature, low-pressure, and high interconnect density inter-die bonding. Post assembly Ni electroless deposited bonding was verified across all inspected diagonal pillars in an area array of 50×50 copper pillars.