C. T. Chong, Lim Teck Guan, Han Yong, F. Che, David Ho Soon Wee, S. Chong
{"title":"面向上两层成型FOWLP封装天线的设计、工艺与可靠性","authors":"C. T. Chong, Lim Teck Guan, Han Yong, F. Che, David Ho Soon Wee, S. Chong","doi":"10.1109/ectc32862.2020.00016","DOIUrl":null,"url":null,"abstract":"Fan-Out WLP with 2-layer molded structure have been proposed for high performance Antenna-in-Package (AiP) for 5G mmWave applications with improved thermal dissipation capability. MMIC chip is embedded in lower mold compound layer with chip facing up to enable the backside of chip to be designed with direct connection to thermal solution to PCB. The feedlines are implemented in-between top and bottom Epoxy Molding Compound (EMC) layers and there can be enhanced with ground layer for minimizing interference from antenna to RF feedline and MMIC. The electrical, mechanical and thermal design considerations, process integration and package reliability are described.","PeriodicalId":6722,"journal":{"name":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"19-24"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design, Process and Reliability of Face-up 2-layer molded FOWLP Antenna-in-Package\",\"authors\":\"C. T. Chong, Lim Teck Guan, Han Yong, F. Che, David Ho Soon Wee, S. Chong\",\"doi\":\"10.1109/ectc32862.2020.00016\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fan-Out WLP with 2-layer molded structure have been proposed for high performance Antenna-in-Package (AiP) for 5G mmWave applications with improved thermal dissipation capability. MMIC chip is embedded in lower mold compound layer with chip facing up to enable the backside of chip to be designed with direct connection to thermal solution to PCB. The feedlines are implemented in-between top and bottom Epoxy Molding Compound (EMC) layers and there can be enhanced with ground layer for minimizing interference from antenna to RF feedline and MMIC. The electrical, mechanical and thermal design considerations, process integration and package reliability are described.\",\"PeriodicalId\":6722,\"journal\":{\"name\":\"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"1 1\",\"pages\":\"19-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ectc32862.2020.00016\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 70th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ectc32862.2020.00016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design, Process and Reliability of Face-up 2-layer molded FOWLP Antenna-in-Package
Fan-Out WLP with 2-layer molded structure have been proposed for high performance Antenna-in-Package (AiP) for 5G mmWave applications with improved thermal dissipation capability. MMIC chip is embedded in lower mold compound layer with chip facing up to enable the backside of chip to be designed with direct connection to thermal solution to PCB. The feedlines are implemented in-between top and bottom Epoxy Molding Compound (EMC) layers and there can be enhanced with ground layer for minimizing interference from antenna to RF feedline and MMIC. The electrical, mechanical and thermal design considerations, process integration and package reliability are described.