Strategies relating to CMP for die to wafer interconnects utilizing hybrid direct bonding

In this study we examine a split-foundry multilevel application specific integrated circuit (ASIC) Si-interposer and die bonded using the direct bond interface (DBI) process, in addition to shortloop vehicles. The designs have been subject to relaxed pattern density rules, and exhibit chemical mechanical planarization (CMP) systematic process issues of varying degrees. We find that the interconnect formation is robust against moderate dielectric thickness variation, as well as a moderate degree of copper corrosion. We discuss and demonstrate various CMP methods which have a clear and repeatable impact. Pattern density effects and defectivity on the bond quality are examined using focused ion beam scanning electron microscope (FIB-SEM) images at the feature scale (sub 100 um) and intra-die scale (few mm). Impact to the CMP performance, including plug recess, and defectivity are discussed.