Irregular Bumps Design Planning for Modern Ball Grid Array Packages

Abstract

In modern flip-chip packages, bumps are often placed irregularly due to different design needs. It costs a great amount of time and manual effort to generate substrate routing from bumps through vias to package balls. Moreover, any single model in prior works could not be simultaneously applied between bumps, vias and balls. In this work, we propose a unified flow network model to formulate the 2-layer substrate routing problem on irregular package structure. We present a renovated bump model that can handle irregular bump plans, filling the gap/insufficiency in existing models. With our methodology, signal assignment on vias and balls, and substrate routing on two layers can be obtained at the same time. We also present an iterative optimization technique to further improve wire congestion. Our results show that the proposed method completes via and ball assignment efficiently, and obtain 100% routability while improving 16.45% in wirelength, compared with manual design in real industrial cases.