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2019 Symposium on VLSI Circuits最新文献

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A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors 用于可穿戴PPG/NIRS传感器的196μW、119dB动态范围的可重构光-数转换器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778004
Qiuyang Lin, Jiawei Xu, Shuang Song, Arjan Breeschoten, M. Konijnenburg, Mingyi Chen, C. Hoof, F. Tavernier, N. V. Helleputte
{"title":"A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors","authors":"Qiuyang Lin, Jiawei Xu, Shuang Song, Arjan Breeschoten, M. Konijnenburg, Mingyi Chen, C. Hoof, F. Tavernier, N. V. Helleputte","doi":"10.23919/VLSIC.2019.8778004","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778004","url":null,"abstract":"This paper presents a low power, reconfigurable, high dynamic range (DR), light-to-digital converter (LDC) for wearable PPG/NIRS recording. The LDC converts light into the time domain with a dual-slope mode integrator, followed by a counter-based time-to-digital converter. This architecture merges the functionalities of a conventional transimpedance amplifier and ADC, while quantization in time domain significantly improves the DR. The inherent low pulse repetition frequency (PRF) of LDC also reduces the LED power. Furthermore, the DR of the LDC can be easily reconfigured by re-programming the counting step size or the PRF of the LEDs, allowing optimal power consumption for different DR scenarios. The IC achieves a maximum DR of 119dB while only consuming $196 mu mathrm {W}($ including 2X LEDs). The IC is validated with PPG and NIRS tests, using photodiodes (PDs) and silicon photomultipliers (SiPMs) respectively.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"240 1","pages":"C58-C59"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77415285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET 7nm FinFET中具有电压预移位CTLE和10抽头DFE的56Gb/s PAM-4接收器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777992
Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, K. Hsieh
{"title":"A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET","authors":"Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, K. Hsieh","doi":"10.23919/VLSIC.2019.8777992","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777992","url":null,"abstract":"A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offset added on top of the differential data signal to alleviate front end nonlinearity. The receiver achieves BER $lt 1 mathrm { E } - 8$ at optimal timing pre-FEC and 0.2UI at 1E-6 BER over 25dB insertion loss at 14GHz. The test-chip consumes 450mW under 1.0V/1.2V power supplies, giving a FoM of 0.321pJ/bit/dB. The active area is 0.352mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"9 1","pages":"C272-C273"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78929946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects 用于低功耗互连的40nm CMOS 52 gb /s Sub-1pJ/bit PAM4接收器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778159
Can Wang, Guang Zhu, Zhao Zhang, C. Yue
{"title":"A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects","authors":"Can Wang, Guang Zhu, Zhao Zhang, C. Yue","doi":"10.23919/VLSIC.2019.8778159","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778159","url":null,"abstract":"This paper presents a source-synchronous PAM4 receiver that adopts quarter-rate topology to achieve good bit efficiency and a voltage-controlled delay line (VCDL) in the reference path of a phase-locked loop (PLL) to recover clock and data. With linear quarter-rate samplers, the equalized input signal by two-stage continuous-time linear equalizer (CTLE) is further equalized by 1tap feed forward equalizer (FFE) embedded in the sampler, and then processed by the following power-efficient dynamic latch and CMOS logics. With the VCDL adjusted by a bang-bang phase detector (BBPD) and a charge pump (CP), the output clocks of the four-stage ring oscillator (RO) based PLL have equal phase spacing and track the input data accordingly. The 40-nm CMOS receiver IC achieves error-free operation at 52 Gb/s with a superior bit efficiency of 0.92 pJ/b while compensating for 7.3-dB channel loss at 13 GHz.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"62 1","pages":"C274-C275"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79491753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication 用于太比特高密度应用的银离子存储电池技术
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778071
S. Fujii, R. Ichihara, T. Konno, M. Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Y. Yoshimura, M. Saitoh, M. Koyama
{"title":"Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication","authors":"S. Fujii, R. Ichihara, T. Konno, M. Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Y. Yoshimura, M. Saitoh, M. Koyama","doi":"10.23919/VLSIC.2019.8778071","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778071","url":null,"abstract":"We demonstrated a cross-point memory array composed of 40nm Ag ionic memory cell with sub- μ A and selectorless operation and 10-year data retention, making it a promising candidate for terabit-scale high-density memory application. Discontinuous conductive path with large and dense Ag clusters enabled 10-year retention even at sub- μ A current with keeping high non-linearity in I-V. We implemented, for the first time, the improved cell into a 40nm cross-point array and demonstrated narrow read distribution which satisfies requirements for reliable array operation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"145 7 1","pages":"T188-T189"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83080688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture 基于异构核心结构的1.32 TOPS/W高能效深度神经网络学习处理器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778006
Donghyeon Han, Jinsu Lee, Jinmook Lee, H. Yoo
{"title":"A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture","authors":"Donghyeon Han, Jinsu Lee, Jinmook Lee, H. Yoo","doi":"10.23919/VLSIC.2019.8778006","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778006","url":null,"abstract":"An energy efficient deep neural network (DNN) learning processor is proposed using direct feedback alignment (DFA). The proposed processor achieves $2.2 times$ faster learning speed compared with the previous learning processors by the pipelined DFA (PDFA). In order to enhance the energy efficiency by 38.7%, the heterogeneous learning core (LC) architecture is optimized with the 11-stage pipeline data-path. Furthermore, direct error propagation core (DEPC) utilizes random number generators (RNG) to remove external memory access (EMA) caused by error propagation (EP) and improve the energy efficiency by 19.9%. The proposed PDFA based learning processor is evaluated on the object tracking (OT) application, and as a result, it shows 34.4 frames-per-second (FPS) throughput with 1.32 TOPS/W energy efficiency.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"19 1","pages":"C304-C305"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85117760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS 具有无限频率检测能力的4- 20gb /s 1.87pJ/b无基准数字CDR
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778157
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, D. Jeong
{"title":"A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS","authors":"Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, D. Jeong","doi":"10.23919/VLSIC.2019.8778157","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778157","url":null,"abstract":"This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is $25 mu mathrm{s}$ with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"83 1","pages":"C194-C195"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83790217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS 1.4 GHz 695千兆Risc-V Inst/s 496核多核处理器，具有网状片上网络和16nm CMOS全数字合成锁相环
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778031
A. Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, S. Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, T. Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, D. Richmond, Zhiru Zhang, I. Galton, C. Batten, M. Taylor, R. Dreslinski
{"title":"A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS","authors":"A. Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, S. Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, T. Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, D. Richmond, Zhiru Zhang, I. Galton, C. Batten, M. Taylor, R. Dreslinski","doi":"10.23919/VLSIC.2019.8778031","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778031","url":null,"abstract":"This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"113 1","pages":"C30-C31"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88072763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition 一个640×640全动态CMOS图像传感器，用于始终在线的物体识别
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778169
Injun Park, W. Jo, Chanmin Park, Byungchoul Park, Jimin Cheon, Youngcheol Chae
{"title":"A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition","authors":"Injun Park, W. Jo, Chanmin Park, Byungchoul Park, Jimin Cheon, Youngcheol Chae","doi":"10.23919/VLSIC.2019.8778169","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778169","url":null,"abstract":"This paper presents a $640times 640$ fully dynamic CMOS image sensor for always-on object recognition. A pixel output is sampled with a dynamic source follower (SF) into a parasitic column capacitor, which is readout by a dynamic single-slope (SS) ADC based on a dynamic bias comparator and an energy-efficient two-step counter. The sensor, implemented in a 0.11μm CMOS, achieves 0.3% peak non-linearity, 6.8$e_{rms}^{-}$ RN and 67dB DR. Its power consumption is only 2.1mW at 44fps and is further reduced to 260μW at 15fps with sub-sampled 320 × 320 mode. This work achieves the state-of-the-art energy-efficiency FoM of 0.7$e^{-}cdot$ nJ.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"40 1","pages":"C214-C215"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83581601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process 10nm制程长通道112 Gb/s PAM4 ADC SERDES接收机
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778136
Yoel Krupnik, Y. Perelman, Itamar Levin, Yosi Sanhedrai, Ro'ee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen
{"title":"112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process","authors":"Yoel Krupnik, Y. Perelman, Itamar Levin, Yosi Sanhedrai, Ro'ee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen","doi":"10.23919/VLSIC.2019.8778136","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778136","url":null,"abstract":"A 112 Gb/s PAM4 ADC based SERDES receiver is implemented on Intel 10 nm FinFET process. The receiver consists of a low noise analog front end (AFE), a 64-way time interleaved analog to digital converter (ADC) and a clock/data recovery (CDR) loop utilizing a 7GHz digitally controlled oscillator (DCO). The receiver supports long reach, -35 dB at Nyquist, channels with a pre-forward error correction bit error rate (BER) $lt 1mathrm{e} -6$ making it compatible with existing and projected Reed-Solomon FEC.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"18 1","pages":"C266-C267"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74183284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth 24mW斩波CTDSM在250kHz带宽下实现103.5dB SNDR和107.5dB DR
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778026
R. Theertham, Prasanth Koottala, Sujith Billa, S. Pavan
{"title":"A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth","authors":"R. Theertham, Prasanth Koottala, Sujith Billa, S. Pavan","doi":"10.23919/VLSIC.2019.8778026","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778026","url":null,"abstract":"We present a CT$Delta Sigma$ M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the reference path. $1/ f$ noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"7 1","pages":"C226-C227"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79495994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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