{"title":"10nm制程长通道112 Gb/s PAM4 ADC SERDES接收机","authors":"Yoel Krupnik, Y. Perelman, Itamar Levin, Yosi Sanhedrai, Ro'ee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen","doi":"10.23919/VLSIC.2019.8778136","DOIUrl":null,"url":null,"abstract":"A 112 Gb/s PAM4 ADC based SERDES receiver is implemented on Intel 10 nm FinFET process. The receiver consists of a low noise analog front end (AFE), a 64-way time interleaved analog to digital converter (ADC) and a clock/data recovery (CDR) loop utilizing a 7GHz digitally controlled oscillator (DCO). The receiver supports long reach, -35 dB at Nyquist, channels with a pre-forward error correction bit error rate (BER) $\\lt 1\\mathrm{e} -6$ making it compatible with existing and projected Reed-Solomon FEC.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"18 1","pages":"C266-C267"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process\",\"authors\":\"Yoel Krupnik, Y. Perelman, Itamar Levin, Yosi Sanhedrai, Ro'ee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen\",\"doi\":\"10.23919/VLSIC.2019.8778136\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 112 Gb/s PAM4 ADC based SERDES receiver is implemented on Intel 10 nm FinFET process. The receiver consists of a low noise analog front end (AFE), a 64-way time interleaved analog to digital converter (ADC) and a clock/data recovery (CDR) loop utilizing a 7GHz digitally controlled oscillator (DCO). The receiver supports long reach, -35 dB at Nyquist, channels with a pre-forward error correction bit error rate (BER) $\\\\lt 1\\\\mathrm{e} -6$ making it compatible with existing and projected Reed-Solomon FEC.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"18 1\",\"pages\":\"C266-C267\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778136\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process
A 112 Gb/s PAM4 ADC based SERDES receiver is implemented on Intel 10 nm FinFET process. The receiver consists of a low noise analog front end (AFE), a 64-way time interleaved analog to digital converter (ADC) and a clock/data recovery (CDR) loop utilizing a 7GHz digitally controlled oscillator (DCO). The receiver supports long reach, -35 dB at Nyquist, channels with a pre-forward error correction bit error rate (BER) $\lt 1\mathrm{e} -6$ making it compatible with existing and projected Reed-Solomon FEC.
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