Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, D. Jeong
{"title":"具有无限频率检测能力的4- 20gb /s 1.87pJ/b无基准数字CDR","authors":"Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, D. Jeong","doi":"10.23919/VLSIC.2019.8778157","DOIUrl":null,"url":null,"abstract":"This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is $25 \\mu \\mathrm{s}$ with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"83 1","pages":"C194-C195"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS\",\"authors\":\"Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, D. Jeong\",\"doi\":\"10.23919/VLSIC.2019.8778157\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is $25 \\\\mu \\\\mathrm{s}$ with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"83 1\",\"pages\":\"C194-C195\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778157\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS
This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is $25 \mu \mathrm{s}$ with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
