发布求助
文献互助 智能选刊 最新文献

2019 Symposium on VLSI Circuits最新文献

筛选
英文 中文
112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process 10nm制程长通道112 Gb/s PAM4 ADC SERDES接收机
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778136
Yoel Krupnik, Y. Perelman, Itamar Levin, Yosi Sanhedrai, Ro'ee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen
{"title":"112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process","authors":"Yoel Krupnik, Y. Perelman, Itamar Levin, Yosi Sanhedrai, Ro'ee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen","doi":"10.23919/VLSIC.2019.8778136","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778136","url":null,"abstract":"A 112 Gb/s PAM4 ADC based SERDES receiver is implemented on Intel 10 nm FinFET process. The receiver consists of a low noise analog front end (AFE), a 64-way time interleaved analog to digital converter (ADC) and a clock/data recovery (CDR) loop utilizing a 7GHz digitally controlled oscillator (DCO). The receiver supports long reach, -35 dB at Nyquist, channels with a pre-forward error correction bit error rate (BER) $lt 1mathrm{e} -6$ making it compatible with existing and projected Reed-Solomon FEC.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"18 1","pages":"C266-C267"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74183284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth 24mW斩波CTDSM在250kHz带宽下实现103.5dB SNDR和107.5dB DR
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778026
R. Theertham, Prasanth Koottala, Sujith Billa, S. Pavan
{"title":"A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth","authors":"R. Theertham, Prasanth Koottala, Sujith Billa, S. Pavan","doi":"10.23919/VLSIC.2019.8778026","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778026","url":null,"abstract":"We present a CT$Delta Sigma$ M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the reference path. $1/ f$ noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"7 1","pages":"C226-C227"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79495994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET 7nm FinFET的56Gb/s长距离全自适应有线PAM-4收发器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778051
D. Pfaff, Shahaboddin Moazzeni, L. Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, R. Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, F. Kuo, Wei-Li Chen, Tae Young Goh, K. Hsieh
{"title":"A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET","authors":"D. Pfaff, Shahaboddin Moazzeni, L. Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, R. Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, F. Kuo, Wei-Li Chen, Tae Young Goh, K. Hsieh","doi":"10.23919/VLSIC.2019.8778051","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778051","url":null,"abstract":"This 56Gb/s PAM-4 transceiver leverages the high logic density provided by the 7nm FinFET technology through rigorous application of digital design styles: An All-Digital PLL and SST transmitter are combined with a 28GS/s 8b ADC and DSP receiver, with the analog signal processing limited to a two stage front-end. The receiver achieves a raw 1e-7 BER with a-33dB insertion loss channel while consuming 500mW, including the 20-tap FFE and 1-tap DFE equipped DSP section.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"96 1","pages":"C270-C271"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84554814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture 采用pwm -双GRO结构的0.02mm2 100dB-DR阻抗监测IC
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778126
Hyeonho Han, Woojun Choi, Youngcheol Chae
{"title":"A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture","authors":"Hyeonho Han, Woojun Choi, Youngcheol Chae","doi":"10.23919/VLSIC.2019.8778126","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778126","url":null,"abstract":"This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"42 1","pages":"C60-C61"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72689711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration 5Gb/s/引脚16Gb LPDDR4/4X可重构SDRAM，具有高电压保持器和基于预测的快速跟踪ZQ校准
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778102
Jin-Seok Heo, Kihan Kim, Donghun Lee, Chang-Kyo Lee, Daesik Moon, KihongParktandChong-kwon Kim, Jin-Hyeok Baek, Sung-woo Yoon, Hui-Kap Yang, Kyung-Soo Kim, Youngjae Kim, Bok-Gue Park, Su-Jin Park, Joungwook Moon, Jae-Hyung Lee, Y. Park, Soobong Jang, S. Hyun, H. Kwon, J. Choi, Y. Sohn, Seung-Jun Bae, Kwang-il Park, Jung-Bae Lee
{"title":"A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration","authors":"Jin-Seok Heo, Kihan Kim, Donghun Lee, Chang-Kyo Lee, Daesik Moon, KihongParktandChong-kwon Kim, Jin-Hyeok Baek, Sung-woo Yoon, Hui-Kap Yang, Kyung-Soo Kim, Youngjae Kim, Bok-Gue Park, Su-Jin Park, Joungwook Moon, Jae-Hyung Lee, Y. Park, Soobong Jang, S. Hyun, H. Kwon, J. Choi, Y. Sohn, Seung-Jun Bae, Kwang-il Park, Jung-Bae Lee","doi":"10.23919/VLSIC.2019.8778102","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778102","url":null,"abstract":"A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. Providing a reconfigurable LVSTL with a mode detection scheme to support two different DRAM interface standards (LPDDR4/4X) depending on I/O supply voltage $(V_{DDQ})$, a proposed design can maintain the system compatibility and longevity to the legacy controller and the PHY structure. The VHK for LPDDR4 enables the 3.2Gb/s operation in the un-terminated load similar to LPDDR4X by alleviating the inter symbol interference (ISI) through the controlled leakage current. In a ZQ calibration, the proposed ZQ algorithm achieves fast ZQ code searching, the calibration time can be reduced by 30% in PVT variation. Moreover, an internal ZQ calibration (IZQC) is newly adopted to minimize the variation of the driver strength to PVT variation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"60 1","pages":"C114-C115"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85534211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper) 用于高性能计算系统和数据中心的48 V输入0.75 V输出DC-DC转换器电源模块(特邀论文)
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778088
T. Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang
{"title":"A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper)","authors":"T. Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang","doi":"10.23919/VLSIC.2019.8778088","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778088","url":null,"abstract":"The IBM Power Block is a high power density, low cost 48 V input DC-DC converter, designed to source up to 107 A of continuous output current to processors in high performance computing (HPC) and datacenter servers. Peak efficiency for a 0.75 V output is 90.6% at 45 A and 85.1% at 107 A. An active clamp forward converter (ACFC) architecture uses a pair of primary FETs and a pair of secondary FETs, separated by a planar transformer. A custom timing chip provides four gate timing signals, whose delays can be stored in internal fuses or set through a serial interface. Transformer and inductor magnetics are integrated into a single ferrite structure that allows induced electro motive forces (EMFs) to cancel, thereby providing near zero output current ripple at 0.75 V and low ripple 0.5 V to 1.0 V. Designed for 1 U servers, the Power Block has a 13 mm x 16 mm footprint and a 19 mm height. The electrical output contact’s flat top permits mounting a heat sink or cold plate.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"12 1","pages":"C168-C169"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89770426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing Catena:用于移动和嵌入式计算的0.5 v sub -0.4 mw 16核空间阵列加速器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777987
J. P. Cerqueira, Thomas J. Repetti, Y. Pu, S. Priyadarshi, Martha A. Kim, Mingoo Seok
{"title":"Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing","authors":"J. P. Cerqueira, Thomas J. Repetti, Y. Pu, S. Priyadarshi, Martha A. Kim, Mingoo Seok","doi":"10.23919/VLSIC.2019.8777987","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777987","url":null,"abstract":"We present Catena, a programmable 16-core spatial array accelerator supporting workloads for mobile and embedded devices. Deeply scaling supply voltage of such parallel processors could save energy, but alone results in limited savings, as it magnifies the energy waste of underutilized hardware. Therefore, we design Catena with novel circuit and architecture techniques to minimize such energy waste. Thanks to the proposed techniques, the 65-nm CMOS prototype achieves state-of-the-art energy efficiencies across multiple workloads.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"3 1","pages":"C54-C55"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78859707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency 并联sshi整流器和集成MPPT的压电能量收集系统，能量提取效率提高417%，跟踪效率达到97%
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778144
Shuo Li, Abhishek Roy, B. Calhoun
{"title":"A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency","authors":"Shuo Li, Abhishek Roy, B. Calhoun","doi":"10.23919/VLSIC.2019.8778144","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778144","url":null,"abstract":"This work presents an integrated maximum-power-point tracking (MPPT) algorithm and its implementation for the high-performance parallel-synchronized-switch harvesting-on-inductor (SSHI) rectifier, which uses the Perturb and Observe (P&O) method and a proposed power monitor for output power evaluation. Fabricated in 130nm, this piezoelectric energy-harvesting system implements a 417% FOM rectifier with 97% tracking efficiency MPPT, which makes it the first work demonstrating a parallel-SSHI rectifier and high tracking-efficiency MPPT simultaneously.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"589 1","pages":"C324-C325"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78939976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS 基于45nm SOI CMOS单片微环谐振器的激光转发相干10Gb/s BPSK收发器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777962
N. Mehta, Sen Lin, Bozhi Yin, S. Moazeni, V. Stojanović
{"title":"A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS","authors":"N. Mehta, Sen Lin, Bozhi Yin, S. Moazeni, V. Stojanović","doi":"10.23919/VLSIC.2019.8777962","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777962","url":null,"abstract":"This paper demonstrates the first fully integrated coherent binary-phase-shift-keying (BPSK) link using microring resonat(MRR) with forwarded laser LO signal. It is enabled by integration of silicon-photonic blocks like optical DAC based modulator, 3-dB coupler, and MRR-based balanced photodetector (PD) in a monolithic zero-change 45nm SOI CMOS. The link operates at 10 Gb/s with transmitter driver consuming 40fJ/bit and receiver with OMA sensitivity of 15.1dBm consuming 450fJ/bit. The laser-forwarded BPSK link improves the laser power budget by $sim 6$ dB compared to direct detection NRZ link with same components.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"47 1","pages":"C192-C193"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73604505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver -106dBm 33nW位级占空比调谐射频唤醒接收机
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777956
J. Moody, Anjana Dissanayake, Henry L. Bishop, Ruochen Lu, Ningxi Liu, Divya Duvvuri, A. Gao, D. Truesdell, N. S. Barker, S. Gong, B. Calhoun, S. Bowers
{"title":"A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver","authors":"J. Moody, Anjana Dissanayake, Henry L. Bishop, Ruochen Lu, Ningxi Liu, Divya Duvvuri, A. Gao, D. Truesdell, N. S. Barker, S. Gong, B. Calhoun, S. Bowers","doi":"10.23919/VLSIC.2019.8777956","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777956","url":null,"abstract":"This work presents a 33 nW wake-up receiver with -106 dBm sensitivity at 428 MHz. Within-bit duty cycling allows RF gain at nano-watt DC power levels providing 26 dB sensitivity improvement over prior art at iso-power. An RF MEMS filter and an automatic gain and offset control loop suppress noise and reject interference. The receiver can be digitally tuned across DC power, latency, and sensitivity to provide flexible functionality from indoor short range to outdoor long-range applications.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"2 1","pages":"C86-C87"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75336158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信