D. Pfaff, Shahaboddin Moazzeni, L. Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, R. Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, F. Kuo, Wei-Li Chen, Tae Young Goh, K. Hsieh
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引用次数: 9
Abstract
This 56Gb/s PAM-4 transceiver leverages the high logic density provided by the 7nm FinFET technology through rigorous application of digital design styles: An All-Digital PLL and SST transmitter are combined with a 28GS/s 8b ADC and DSP receiver, with the analog signal processing limited to a two stage front-end. The receiver achieves a raw 1e-7 BER with a-33dB insertion loss channel while consuming 500mW, including the 20-tap FFE and 1-tap DFE equipped DSP section.
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