J. P. Cerqueira, Thomas J. Repetti, Y. Pu, S. Priyadarshi, Martha A. Kim, Mingoo Seok
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Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing
We present Catena, a programmable 16-core spatial array accelerator supporting workloads for mobile and embedded devices. Deeply scaling supply voltage of such parallel processors could save energy, but alone results in limited savings, as it magnifies the energy waste of underutilized hardware. Therefore, we design Catena with novel circuit and architecture techniques to minimize such energy waste. Thanks to the proposed techniques, the 65-nm CMOS prototype achieves state-of-the-art energy efficiencies across multiple workloads.
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