Jin-Seok Heo, Kihan Kim, Donghun Lee, Chang-Kyo Lee, Daesik Moon, KihongParktandChong-kwon Kim, Jin-Hyeok Baek, Sung-woo Yoon, Hui-Kap Yang, Kyung-Soo Kim, Youngjae Kim, Bok-Gue Park, Su-Jin Park, Joungwook Moon, Jae-Hyung Lee, Y. Park, Soobong Jang, S. Hyun, H. Kwon, J. Choi, Y. Sohn, Seung-Jun Bae, Kwang-il Park, Jung-Bae Lee
{"title":"A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration","authors":"Jin-Seok Heo, Kihan Kim, Donghun Lee, Chang-Kyo Lee, Daesik Moon, KihongParktandChong-kwon Kim, Jin-Hyeok Baek, Sung-woo Yoon, Hui-Kap Yang, Kyung-Soo Kim, Youngjae Kim, Bok-Gue Park, Su-Jin Park, Joungwook Moon, Jae-Hyung Lee, Y. Park, Soobong Jang, S. Hyun, H. Kwon, J. Choi, Y. Sohn, Seung-Jun Bae, Kwang-il Park, Jung-Bae Lee","doi":"10.23919/VLSIC.2019.8778102","DOIUrl":null,"url":null,"abstract":"A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. Providing a reconfigurable LVSTL with a mode detection scheme to support two different DRAM interface standards (LPDDR4/4X) depending on I/O supply voltage $(V_{DDQ})$, a proposed design can maintain the system compatibility and longevity to the legacy controller and the PHY structure. The VHK for LPDDR4 enables the 3.2Gb/s operation in the un-terminated load similar to LPDDR4X by alleviating the inter symbol interference (ISI) through the controlled leakage current. In a ZQ calibration, the proposed ZQ algorithm achieves fast ZQ code searching, the calibration time can be reduced by 30% in PVT variation. Moreover, an internal ZQ calibration (IZQC) is newly adopted to minimize the variation of the driver strength to PVT variation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"60 1","pages":"C114-C115"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. Providing a reconfigurable LVSTL with a mode detection scheme to support two different DRAM interface standards (LPDDR4/4X) depending on I/O supply voltage $(V_{DDQ})$, a proposed design can maintain the system compatibility and longevity to the legacy controller and the PHY structure. The VHK for LPDDR4 enables the 3.2Gb/s operation in the un-terminated load similar to LPDDR4X by alleviating the inter symbol interference (ISI) through the controlled leakage current. In a ZQ calibration, the proposed ZQ algorithm achieves fast ZQ code searching, the calibration time can be reduced by 30% in PVT variation. Moreover, an internal ZQ calibration (IZQC) is newly adopted to minimize the variation of the driver strength to PVT variation.