T. Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang
{"title":"用于高性能计算系统和数据中心的48 V输入0.75 V输出DC-DC转换器电源模块(特邀论文)","authors":"T. Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang","doi":"10.23919/VLSIC.2019.8778088","DOIUrl":null,"url":null,"abstract":"The IBM Power Block is a high power density, low cost 48 V input DC-DC converter, designed to source up to 107 A of continuous output current to processors in high performance computing (HPC) and datacenter servers. Peak efficiency for a 0.75 V output is 90.6% at 45 A and 85.1% at 107 A. An active clamp forward converter (ACFC) architecture uses a pair of primary FETs and a pair of secondary FETs, separated by a planar transformer. A custom timing chip provides four gate timing signals, whose delays can be stored in internal fuses or set through a serial interface. Transformer and inductor magnetics are integrated into a single ferrite structure that allows induced electro motive forces (EMFs) to cancel, thereby providing near zero output current ripple at 0.75 V and low ripple 0.5 V to 1.0 V. Designed for 1 U servers, the Power Block has a 13 mm x 16 mm footprint and a 19 mm height. The electrical output contact’s flat top permits mounting a heat sink or cold plate.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"12 1","pages":"C168-C169"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper)\",\"authors\":\"T. Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang\",\"doi\":\"10.23919/VLSIC.2019.8778088\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The IBM Power Block is a high power density, low cost 48 V input DC-DC converter, designed to source up to 107 A of continuous output current to processors in high performance computing (HPC) and datacenter servers. Peak efficiency for a 0.75 V output is 90.6% at 45 A and 85.1% at 107 A. An active clamp forward converter (ACFC) architecture uses a pair of primary FETs and a pair of secondary FETs, separated by a planar transformer. A custom timing chip provides four gate timing signals, whose delays can be stored in internal fuses or set through a serial interface. Transformer and inductor magnetics are integrated into a single ferrite structure that allows induced electro motive forces (EMFs) to cancel, thereby providing near zero output current ripple at 0.75 V and low ripple 0.5 V to 1.0 V. Designed for 1 U servers, the Power Block has a 13 mm x 16 mm footprint and a 19 mm height. The electrical output contact’s flat top permits mounting a heat sink or cold plate.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"12 1\",\"pages\":\"C168-C169\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778088\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778088","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
IBM Power Block是一款高功率密度、低成本的48v输入DC-DC转换器,旨在为高性能计算(HPC)和数据中心服务器中的处理器提供高达107 a的连续输出电流。0.75 V输出的峰值效率在45 a时为90.6%,在107 a时为85.1%。有源箝位正激变换器(ACFC)结构使用一对主场效应管和一对次场效应管,由一个平面变压器分隔。定制定时芯片提供四个门定时信号,其延迟可以存储在内部保险丝或通过串行接口设置。变压器和电感器的磁性集成到一个单一的铁氧体结构中,允许感应电动势(emf)抵消,从而在0.75 V时提供接近零的输出电流纹波和0.5 V至1.0 V的低纹波。Power Block适用于1u服务器,尺寸为13mm × 16mm,高19mm。电输出触点的平顶允许安装散热器或冷板。
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper)
The IBM Power Block is a high power density, low cost 48 V input DC-DC converter, designed to source up to 107 A of continuous output current to processors in high performance computing (HPC) and datacenter servers. Peak efficiency for a 0.75 V output is 90.6% at 45 A and 85.1% at 107 A. An active clamp forward converter (ACFC) architecture uses a pair of primary FETs and a pair of secondary FETs, separated by a planar transformer. A custom timing chip provides four gate timing signals, whose delays can be stored in internal fuses or set through a serial interface. Transformer and inductor magnetics are integrated into a single ferrite structure that allows induced electro motive forces (EMFs) to cancel, thereby providing near zero output current ripple at 0.75 V and low ripple 0.5 V to 1.0 V. Designed for 1 U servers, the Power Block has a 13 mm x 16 mm footprint and a 19 mm height. The electrical output contact’s flat top permits mounting a heat sink or cold plate.