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2019 Symposium on VLSI Circuits最新文献

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An Automatic Ear Detection Technique in Capacitive Sensing Readout IC Using Cascaded Classifiers and Hovering function 基于级联分类器和悬停功能的电容式读出集成电路耳部自动检测技术
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778125
Seunghoon Ko
{"title":"An Automatic Ear Detection Technique in Capacitive Sensing Readout IC Using Cascaded Classifiers and Hovering function","authors":"Seunghoon Ko","doi":"10.23919/VLSIC.2019.8778125","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778125","url":null,"abstract":"We report a capacitance sensing circuit-based ear recognition technique that can lead to an introduction of bezel-less smart phone. The designed chip is fabricated with 130nm technology. The fundamental functionality of pseudo high voltage driving analog front end (AFE) is demonstrated. We also discuss the detection algorithm consisting of weak and strong classifiers. The measurement result showed the feasibility of replacing an existing proximity sensor with detection rate of 83%.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"115 1","pages":"C218-C219"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80340444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Sub-pA Current Sensing Front-End for Transient Induced Molecular Spectroscopy 一种用于瞬态诱导分子光谱的亚pa电流传感前端
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777980
Da Ying, Ping-Wei Chen, Chi-Yang Tseng, Y. Lo, D. Hall
{"title":"A Sub-pA Current Sensing Front-End for Transient Induced Molecular Spectroscopy","authors":"Da Ying, Ping-Wei Chen, Chi-Yang Tseng, Y. Lo, D. Hall","doi":"10.23919/VLSIC.2019.8777980","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777980","url":null,"abstract":"We report an 8-channel array of low-noise (30.3fA/√Hz) current sensing front-ends with on-chip sensors for label-free, restriction-free biosensing. The analog front-end (AFE) consists of a 1st-order continuous-time delta-sigma (CT-ΔΣ) modulator that achieves 123fA sensitivity and 139dB cross-scale dynamic range over a 10Hz bandwidth while consuming 50 μW and occupying 0.11mm2 per channel. A digital IIR filter and a tri-level pulse width modulated (PWM) current-steering DAC are used to realize the equivalent performance of a multi-bit ΔΣ in an area/power efficient manner. This platform was used to observe protein-ligand interactions in real-time.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"30 1","pages":"C316-C317"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83666373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution 具有11位分辨率的CMOS温度稳定二维机械应力传感器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778132
Umidjon Nurmetov, Tobias Fritz, Ernst Müllner, Christopher M. Dougherty, F. Kreupl, R. Brederlow
{"title":"A CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution","authors":"Umidjon Nurmetov, Tobias Fritz, Ernst Müllner, Christopher M. Dougherty, F. Kreupl, R. Brederlow","doi":"10.23919/VLSIC.2019.8778132","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778132","url":null,"abstract":"An integrated 11-bit 2-D CMOS stress sensor is presented with 66dB of dynamic range, measuring -100 to 360MPa, and < 1LSB error over temperature from 5°C to 90°C. N-Well-based primary elements enable accurate sensing of stress magnitude and angle, and allow repeatable error compensation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"117 1","pages":"C64-C65"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75719400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 10-MHz 14.3W/mm2 DAB Hysteretic Control Power Converter Achieving 2.5W/247ns Full Load Power Flipping and above 80% Efficiency in 99.9% Power Range for 5G IoTs 10mhz 14.3W/mm2 DAB迟滞控制功率转换器，实现2.5W/247ns满负荷功率翻转，在99.9%的功率范围内实现80%以上的效率，用于5G物联网
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778192
Kang Wei, Bumkil Lee, D. Ma
{"title":"A 10-MHz 14.3W/mm2 DAB Hysteretic Control Power Converter Achieving 2.5W/247ns Full Load Power Flipping and above 80% Efficiency in 99.9% Power Range for 5G IoTs","authors":"Kang Wei, Bumkil Lee, D. Ma","doi":"10.23919/VLSIC.2019.8778192","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778192","url":null,"abstract":"A double adaptive bound (DAB) hysteretic control power converter is designed for 5G IoTs, which require nanosecond power load flipping and high efficiency across full power range. In response to 1A/3ns load step-up/step-down, it achieves 1% $mathrm{t}_{settle}$ of 247ns/387ns, thanks to the DAB control. This is 6× faster than the best of the arts on $0.18 mu mathrm{m}$ CMOS. A synchronized DCR offset cancellation scheme improves $V_{O}$ regulation accuracy by 10×. As power scales from full to ultra-light load, the controller self-reconfigures to remove redundant controller loss and facilitate adaptive system power delivery. It achieves $gt80$% efficiency over 99.9% of 2.5W full power range. Highly efficient design leads to the highest reported chip power density of 14.3W/mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"46 1","pages":"C172-C173"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75488678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW 集成电源管理和微控制器的超宽功率自适应低至西北
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778085
Longyang Lin, Saurabh Jain, M. Alioto
{"title":"Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW","authors":"Longyang Lin, Saurabh Jain, M. Alioto","doi":"10.23919/VLSIC.2019.8778085","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778085","url":null,"abstract":"This paper presents a power management unit (PMU) driving a microcontroller, and controlling a power knob that enables adaptation to the sensed power availability over an ultra-wide range, well beyond voltage scaling. Conventional battery-powered operation is augmented with pure harvesting. Wide power adaptation is enabled by comparator delay selfbiasing and zero-current switching scheme shared among all power modes with single-cycle convergence.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"22 1","pages":"C178-C179"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78139205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Two-Phase 2MHz DSD GaN Power Converter with Master-Slave AO2T Control for Direct 48V/1V DC-DC Conversion 用于直接48V/1V DC-DC转换的具有主从AO2T控制的两相2MHz DSD GaN功率转换器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778017
Dong Yan, Xugang Ke, D. Ma
{"title":"A Two-Phase 2MHz DSD GaN Power Converter with Master-Slave AO2T Control for Direct 48V/1V DC-DC Conversion","authors":"Dong Yan, Xugang Ke, D. Ma","doi":"10.23919/VLSIC.2019.8778017","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778017","url":null,"abstract":"This paper reports a GaN power converter that achieves direct 48V/1V DC-DC voltage conversion with a two-phase DSD architecture at 2MHz, pushing the minimum duty ratio to a record low level of 2.1%. The AO2T control with elastic ON-time modulator leads to significant improvement on transient response and voltage droop performance, compared to prior arts. A master phase mirror enables adaptive master-slave phase operation, accomplishing automatic phase current balancing for improved reliability. The converter achieves a peak efficiency of 85.4%, with an active die of 1.46mm2 on 180nm HV BCD process.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"3 1","pages":"C170-C171"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90199126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS 一种具有不固定分接加权特性的0.87 V 12.5 Gb/s时钟路径反馈均衡接收机
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777968
Daewoong Lee, Dongil Lee, Yong-Hun Kim, L. Kim
{"title":"A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS","authors":"Daewoong Lee, Dongil Lee, Yong-Hun Kim, L. Kim","doi":"10.23919/VLSIC.2019.8777968","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777968","url":null,"abstract":"This paper presents a clock-path feedback equalization receiver with unfixed tap weighting property. In the proposed receiver, an equalization operation is achieved through a clock path so that a feedback loop delay is improved. Moreover, a feedback weight is changeable depending on the amount of inter-symbol interference (ISI) resulting in that a single tap compensates a high channel loss. Fabricated in a 65 nm CMOS, the receiver achieves a power efficiency of 0.376 mW/Gbps at a data rate of 12.5 Gb/s in 0.87 V supply. A BER <10-12 for an eye width of 0.16 UI was verified over a 19 dB PCB channel loss. The figure of merit (FoM) is 0.0198 mW/Gbps/dB and the receiver occupies 0.00294 mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"2 1","pages":"C196-C197"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86429756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking 250Mv, 0.063J/Ghash的14nm CMOS比特币挖掘引擎，具有双vcc Sha256数据路径和基于三相锁存器的时钟
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777966
Vikram B. Suresh, Sudhir K. Satpathy, Raghavan Kumar, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy, V. De, S. Mathew
{"title":"A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking","authors":"Vikram B. Suresh, Sudhir K. Satpathy, Raghavan Kumar, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy, V. De, S. Mathew","doi":"10.23919/VLSIC.2019.8777966","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777966","url":null,"abstract":"A 0.15mm2 Bitcoin mining engine is fabricated in 14nm CMOS with highest-reported energy-efficiency of 0.063J/GHash at 250mV, $25 ^{circ}mathrm {C}$. Fully-unrolled SHA256 datapath with Bitcoin-specific look-ahead/deferred digest optimizations and 3-cycle distributed scheduler provide 31/56% digest/scheduler delay reductions, resulting in 10% higher energy-efficiency with dual-Vcc operation. 3-phase latch-based clocking with stretchable non-overlapping clocks eliminates all min-delay paths, reducing total sequential power consumption by 50%. Robust mining operation over a wide supply range of 230–900mV is demonstrated, with 10–760MHash/s throughput measured at $100 ^{circ}mathrm {C}$.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"263 1","pages":"C32-C33"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89193444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The PCM way for embedded Non Volatile Memories applications 嵌入式非易失性存储器应用的PCM方法
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777957
P. Zuliani, A. Conte, P. Cappelletti
{"title":"The PCM way for embedded Non Volatile Memories applications","authors":"P. Zuliani, A. Conte, P. Cappelletti","doi":"10.23919/VLSIC.2019.8777957","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777957","url":null,"abstract":"A comparative analysis of different Resistive Memories proposed as Non Volatile Memories for embedded applications is here presented. Based on today scenario of industry-standard Floating Gate solutions, key factors as performances, reliability and technology maturity are considered when facing more innovative memory cells. In particular the race seems to be open at 28nm, where different players are proposing different memories integrated in the Back End Of the Line. Original results obtained on multi-megabits array integrating Phase Change Memories are here discussed covering cell scalability, High Temperature data retention and extended endurance capability, all in line with eNVM application requirements.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"3 1","pages":"T192-T193"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89235942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Announcements: Future conferences] [公告:未来会议]
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8778168
{"title":"[Announcements: Future conferences]","authors":"","doi":"10.23919/vlsic.2019.8778168","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8778168","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"25 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89799972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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