A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS

This paper presents a clock-path feedback equalization receiver with unfixed tap weighting property. In the proposed receiver, an equalization operation is achieved through a clock path so that a feedback loop delay is improved. Moreover, a feedback weight is changeable depending on the amount of inter-symbol interference (ISI) resulting in that a single tap compensates a high channel loss. Fabricated in a 65 nm CMOS, the receiver achieves a power efficiency of 0.376 mW/Gbps at a data rate of 12.5 Gb/s in 0.87 V supply. A BER <10-12 for an eye width of 0.16 UI was verified over a 19 dB PCB channel loss. The figure of merit (FoM) is 0.0198 mW/Gbps/dB and the receiver occupies 0.00294 mm2.