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2019 Symposium on VLSI Circuits最新文献

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A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET 16nm FinFET 50Gb/s混合集成硅光子光链路
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778047
M. Raj, Y. Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, Jimmy Grayson, M. Epitaux, Ken Chang
{"title":"A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET","authors":"M. Raj, Y. Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, Jimmy Grayson, M. Epitaux, Ken Chang","doi":"10.23919/VLSIC.2019.8778047","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778047","url":null,"abstract":"This work presents an Electro-Absorption Modulator (EAM) based single-mode 50Gb/s NRZ optical link in 16nm FinFET. The TX uses T-coil based over-peaking to improve modulation efficiency and relax TIA’s bandwidth and noise requirement. The RX uses a 3-stage TIA with T-coils to improve BW. The link sensitivity is -10.9dBm OMA at BER $lt 10^{-12}$ and it consumes 4.31pJ/bit at 50Gb/s with 2dB link margin.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"127 1","pages":"C190-C191"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72949788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Joint Evening Panel Discussion: The Semiconductor Industry at a Tipping Point: What’s Next? 联合晚间小组讨论:半导体行业的转折点:下一步是什么?
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8778127
{"title":"Joint Evening Panel Discussion: The Semiconductor Industry at a Tipping Point: What’s Next?","authors":"","doi":"10.23919/vlsic.2019.8778127","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8778127","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"45 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88830069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-efficient continual learning in hybrid supervised-unsupervised neural networks with PCM synapses 具有PCM突触的有监督-无监督混合神经网络的节能持续学习
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778001
S. Bianchi, I. Muñoz-Martín, G. Pedretti, O. Melnic, S. Ambrogio, Daniele Ielmini
{"title":"Energy-efficient continual learning in hybrid supervised-unsupervised neural networks with PCM synapses","authors":"S. Bianchi, I. Muñoz-Martín, G. Pedretti, O. Melnic, S. Ambrogio, Daniele Ielmini","doi":"10.23919/VLSIC.2019.8778001","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778001","url":null,"abstract":"Artificial neural networks (ANNs) can outperform the human ability of object recognition by supervised training of synaptic parameters with large datasets. Contrarily to the human brain, however, ANNs cannot continually learn, i.e. acquire new information without catastrophically forgetting previous knowledge. To solve this issue, we present a novel hybrid neural network based on CMOS logic and phase change memory (PCM) synapses, mixing a supervised convolutional neural network (CNN) with bio-inspired unsupervised learning and neuronal redundancy. We demonstrate high classification accuracy in MNIST and CIFAR10 datasets (98% and 85%, respectively) and energy-efficient continual learning of up to 30% of non-trained classes with 83% average accuracy.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"39 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89303248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Time Domain Artificial Intelligence Radar for Hand Gesture Recognition Using 33-GHz Direct Sampling 基于33-GHz直接采样的时域人工智能手势识别雷达
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777995
Jungwoon Park, Junyoung Jang, Geunhaeng Lee, Hyunmin Koh, Changhwan Kim, Tae Wook Kim
{"title":"A Time Domain Artificial Intelligence Radar for Hand Gesture Recognition Using 33-GHz Direct Sampling","authors":"Jungwoon Park, Junyoung Jang, Geunhaeng Lee, Hyunmin Koh, Changhwan Kim, Tae Wook Kim","doi":"10.23919/VLSIC.2019.8777995","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777995","url":null,"abstract":"This research developed time domain Artificial Intelligence radar using up to 33 GS/s direct sampling technique. It can recognize both static and dynamic hand gesture by learning the unique impulse signal that comes back from target. The algorithm gets recognition rate 93.2% and 90.5%, respectively on set of static and dynamic gesture.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"48 1","pages":"C24-C25"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72651025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur 2.2 ghz 3.2 mw无dtc采样ΔΣ分数n锁相环，带内相位噪声为-110 dBc/Hz，参考杂散为-246dB，参考杂散为-83dBc
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778000
J. Tao, C. Heng
{"title":"A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur","authors":"J. Tao, C. Heng","doi":"10.23919/VLSIC.2019.8778000","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778000","url":null,"abstract":"This paper presents the first sampling ΔΣ fractional-N (frac-N) PLL without the digital-to-time converter (DTC), whose design is challenging and requires complex calibration. It employs a linear slope generator (LSG) to output a linear waveform and this linearization enables the sampling phase detector (SPD) to handle larger phase step from the phase interpolator (PI). This DTC-free 2.2-GHz PLL achieves in-band phase noise of-110 dBc/Hz, - 246-dB FOM and -83dBc reference spur while consuming only 3.2 mW power.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"36 2 1","pages":"C162-C163"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89135785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms 面向异构计算平台的低功耗4GHz 16nm SRAM架构
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778108
Cagla Cakir, A. Chen, Y. Chong, S. Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, M. Bhargava
{"title":"A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms","authors":"Cagla Cakir, A. Chen, Y. Chong, S. Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, M. Bhargava","doi":"10.23919/VLSIC.2019.8778108","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778108","url":null,"abstract":"We present a high-performance 6T SRAM architecture equipped with low-power features of late cancel, left-right enable, input-gating, and power-gating. Measurements show that these SRAMs can support CPUs running at 4GHz while offering dynamic power savings of 17% and 6% for the caches and the system respectively and up to 21X static power system savings for the low-power implementation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"1 1","pages":"C112-C113"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83436822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load 一种支持大数字负载的0.5-1V输入事件驱动多数字低压差稳压系统
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778117
S. Kim, Dongkwun Kim, Y. Pu, Chunlei Shi, Mingoo Seok
{"title":"A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load","authors":"S. Kim, Dongkwun Kim, Y. Pu, Chunlei Shi, Mingoo Seok","doi":"10.23919/VLSIC.2019.8778117","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778117","url":null,"abstract":"Recent digital low-dropout regulators have demonstrated competitive load regulation performance for a digital load even with a low input voltage. However, few existing regulator designs have investigated into supporting a spatially large load with realistic grid parasitics. This paper presents a system consisting of nine digital low-drop-out regulators based on event-driven control for better supporting such load. At 0.5V (1V) input, our prototype improves the load regulation FoM by 3.9X (9.1X) and current density by 8.7X (2.8X) over the prior state of the arts [1, 3, 4].","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"48 1","pages":"C128-C129"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82141188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS 一种64Gb/s 2.29pJ/b的PAM-4 VCSEL发射机，采用65nm CMOS，具有3分路非对称FFE
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777952
Jeongho Hwang, Hong-Seok Choi, H. Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, D. Jeong
{"title":"A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS","authors":"Jeongho Hwang, Hong-Seok Choi, H. Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, D. Jeong","doi":"10.23919/VLSIC.2019.8777952","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777952","url":null,"abstract":"This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"78 1","pages":"C268-C269"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91401237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing 基于数字混频的全数字时偏校准，实现48.5dB信噪比的29mW 5GS/s时交错SAR ADC
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778077
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, Hegong Wei, R. Martins
{"title":"A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing","authors":"Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, Hegong Wei, R. Martins","doi":"10.23919/VLSIC.2019.8778077","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778077","url":null,"abstract":"This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits. We implement the sub-channel SAR with a splitting-combined monotonic switching procedure. The prototype ADC achieves 48.5dB SNDR at Nyquist rate, while the power consumption is 29mW leading to a Walden FOM of 26.7fJ/conv-step.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"120 1","pages":"C76-C77"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77152733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
VLSI Circuits 2019 Session Quick Index VLSI电路2019会议快速索引
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8778111
{"title":"VLSI Circuits 2019 Session Quick Index","authors":"","doi":"10.23919/vlsic.2019.8778111","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8778111","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"41 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82385725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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