A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur

This paper presents the first sampling ΔΣ fractional-N (frac-N) PLL without the digital-to-time converter (DTC), whose design is challenging and requires complex calibration. It employs a linear slope generator (LSG) to output a linear waveform and this linearization enables the sampling phase detector (SPD) to handle larger phase step from the phase interpolator (PI). This DTC-free 2.2-GHz PLL achieves in-band phase noise of-110 dBc/Hz, - 246-dB FOM and -83dBc reference spur while consuming only 3.2 mW power.