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2019 Symposium on VLSI Circuits最新文献

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A 108dB DR Hybrid-CTDT Direct-Digitalization ΔΣ-ΣM Front-End with 720mVpp Input Range and >300mV Offset Removal for Wearable Bio-Signal Recording 108dB DR Hybrid-CTDT直接数字化ΔΣ-ΣM前端，720mVpp输入范围和>300mV偏移去除，可穿戴生物信号记录
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778185
Xiaolin Yang, Jiawei Xu, Hosung Chun, M. Ballini, Menglian Zhao, Xiaobo Wu, C. Hoof, N. V. Helleputte
{"title":"A 108dB DR Hybrid-CTDT Direct-Digitalization ΔΣ-ΣM Front-End with 720mVpp Input Range and >300mV Offset Removal for Wearable Bio-Signal Recording","authors":"Xiaolin Yang, Jiawei Xu, Hosung Chun, M. Ballini, Menglian Zhao, Xiaobo Wu, C. Hoof, N. V. Helleputte","doi":"10.23919/VLSIC.2019.8778185","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778185","url":null,"abstract":"This paper presents a direct-digitalization front-end for wearable bio-signal recording. The proposed front-end is built with a 2nd order hybrid-CTDT $Delta Sigma - Sigma$ modulator, taking the benefits of oversampling and noise shaping. The $Delta Sigma - Sigma$ topology removes electrode DC offset and shapes signals as well as motion artifacts at the input by adding $aSigma -$stage in the feedback loop, while the $Sigma -$stage recovers the bio-signals by quantizing the difference of the consecutive samples. To meet the requirements of noise, input impedance of a bio-potential interface, a capacitively-coupled chopper amplifier serves as an input stage and also an active adder. An asynchronous 5-bit differential-difference SAR quantizer combines the functionalities of a coarse ADC and a passive adder in a traditional $Delta Sigma$ loop, leading to a compact output stage. The prototype IC is fabricated in a standard TSMC $0.18 mu m$ CMOS process and achieves the peak SNR of 105.6dB and DR of 108.3dB with the maximum linear input range of 720mVpp. Its input referred noise is $0.98 mu $ Vrms over 100Hz bandwidth. ECG and EEG measurements verify the bio-potential signals acquisition capability of this IC.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"26 1","pages":"C296-C297"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90738243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques 具有CC-CV充电和片上引导技术的6.78MHz 92.3%峰值效率单级无线充电器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777990
Lin Cheng, Xinyuan Ge, Wai Chiu Ng, W. Ki, Jiawei Zheng, T. Kwok, C. Tsui, Ming Liu
{"title":"A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques","authors":"Lin Cheng, Xinyuan Ge, Wai Chiu Ng, W. Ki, Jiawei Zheng, T. Kwok, C. Tsui, Ming Liu","doi":"10.23919/VLSIC.2019.8777990","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777990","url":null,"abstract":"A fully-integrated wireless charger that realizes voltage rectification, voltage regulation and CC-CV charging in a single power stage is proposed to achieve high efficiency and low cost and volume. A bootstrapping technique is also proposed to integrate bootstrap capacitors on-chip. The charger was designed in a standard 0.35 μm CMOS process with a die area of 8mm2, and the measured peak efficiency reaches 92.3% and 91.4% when the charging currents are 1A and 1.5A, respectively.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"143 1","pages":"C320-C321"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85349420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS 一个71年。采用时间交错噪声整形量化器的4dB SNDR 30MHz BW连续Delta-sigma调制器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777949
Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang
{"title":"A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS","authors":"Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang","doi":"10.23919/VLSIC.2019.8777949","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777949","url":null,"abstract":"This work presents a continuous-time delta-sigma modulator (CTDSM) using a time-interleaved noise-shaping quantizer targeted for wireless communication system application. A quantization error duplication method enables the SAR-based quantizer to implement noise-shaping and operate at an 832MHz sampling frequency concurrently. Through the use of a CRFB loop filter topology and the noise-shaping quantizer, the proposed CTDSM achieves 71.4 dB SNDR in 30-MHz BW without STF peaking. The FoMs and FoMw are 171 dB and 17.6 fJ/conv.-step, respectively.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"36 1","pages":"C228-C229"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82449772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI 嵌入式PCM宏用于28nm FD-SOI的汽车级微控制器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778129
F. Disegni, R. Annunziata, A. Molgora, G. Campardo, P. Cappelletti, P. Zuliani, P. Ferreira, A. Ventre, Giuseppe Castagna, A. Cathelin, A. Gandolfo, F. Goller, S. Malhi, D. Manfrè, A. Maurelli, C. Torti, F. Arnaud, M. Carfì, M. Perroni, M. Caruso, S. Pezzini, G. Piazza, O. Weber, M. Peri
{"title":"Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI","authors":"F. Disegni, R. Annunziata, A. Molgora, G. Campardo, P. Cappelletti, P. Zuliani, P. Ferreira, A. Ventre, Giuseppe Castagna, A. Cathelin, A. Gandolfo, F. Goller, S. Malhi, D. Manfrè, A. Maurelli, C. Torti, F. Arnaud, M. Carfì, M. Perroni, M. Caruso, S. Pezzini, G. Piazza, O. Weber, M. Peri","doi":"10.23919/VLSIC.2019.8778129","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778129","url":null,"abstract":"The paper proposes a BEOL PCM-based e-NVM solution integrated in a 28nm FD-SOI CMOS technology, giving excellent performances in terms of area, read and write time and temperature range. The integration of a 6MB PCM in an automotive grade (Tj up to 165C) microcontroller chip is presented here, exhibiting a robust solution satisfying all criteria of the demanding automotive environment. The Gex Sby Tez material used for the PCM [1] has been tuned to reach the 165C compliance and 10 years data retention. CMOS 28nm FD-SOI has been determined as the optimal technology to exploit PCM capabilities [2]. Technology also offers full feature 5V devices required for automotive application. Body bias of the FD-SOI allows controlling the quiescent leakage both in circuitry and in the unselected bits inside the memory array, optimizing the functionality.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"56 1","pages":"C204-C205"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84151013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems 4.8GB/s 256Mb(x16)低引脚数DRAM和控制器架构(RPCA)，可降低物联网/可穿戴/TCON/视频/ ai边缘系统的外形尺寸和成本
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778049
C. Shiah, C. N. Chang, R. Crisp, C. P. Lin, C. Pan, C. P. Chuang, H. L. Chen, S. Jheng, T. Chang, W. Huang, K. Ting, Rick Dai, W. Huang, B. Rong, Nicky Lu
{"title":"A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems","authors":"C. Shiah, C. N. Chang, R. Crisp, C. P. Lin, C. Pan, C. P. Chuang, H. L. Chen, S. Jheng, T. Chang, W. Huang, K. Ting, Rick Dai, W. Huang, B. Rong, Nicky Lu","doi":"10.23919/VLSIC.2019.8778049","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778049","url":null,"abstract":"A new breed of Form-Factor-Driven DRAMs offers 80% lower standby power and > 50% IO signal reduction vs. Capacity-Driven commodity DRAM. Command/address/data are multiplexed onto 16 pins and combined with a Serial Control Pin in a Single-Edge-Pinout-Floorplan, providing bus efficiency >98%. Major SOC-DRAM subsystem cost savings are enabled via die size, packaging and PCB area savings using this RPCA. A 100x speedup of array fills using a new Group Write circuit further reduces test cost.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"27 1","pages":"C116-C117"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90165915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications 250mW 5.4 g - novell - pixel /s逼真的全高清五摄像头调焦处理器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778155
Po-Han Chen, Shu-Wen Yang, Shih-Yao Huang, Li-De Chen, Chao-Tsung Huang
{"title":"A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications","authors":"Po-Han Chen, Shu-Wen Yang, Shih-Yao Huang, Li-De Chen, Chao-Tsung Huang","doi":"10.23919/VLSIC.2019.8778155","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778155","url":null,"abstract":"In this paper, we present an integrated circuit which supports Full-HD photorealistic refocusing. In contrast to the conventional single-image blurring, it provides physicallycorrect bokeh effect by rendering and then averaging hundreds of novel views from five images taken in different perspectives. To address the huge requirement of DRAM bandwidth and computing power, we adopt a block-based multi-rate framework and further propose two techniques: four-direction view generation and highly-parallel view rendering. The former provides a compact system architecture to save 32% of SRAM area and 92% of DRAM bandwidth without noticeable quality degradation. The latter efficiently generates 5.4G novel pixels per second to provide high-quality refocusing. This chip is fabricated in 40nm CMOS process, and the core area is 3.61 mm2. It consumes 250mW when operating at 200MHz and 0.9V to support Full-HD photorealistic refocusing up to 40 fps.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"15 1","pages":"C154-C155"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82232847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator 一个0.2 - 8 MS/s的10b柔性SAR ADC，实现0.35 - 2.5 fJ/反步，采用自淬动态偏置比较器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778093
H. S. Bindra, A. Annema, S. Louwsma, B. Nauta
{"title":"A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator","authors":"H. S. Bindra, A. Annema, S. Louwsma, B. Nauta","doi":"10.23919/VLSIC.2019.8778093","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778093","url":null,"abstract":"A 10b flexible SAR ADC is presented incorporating a self-quenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR >66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"20 1","pages":"C74-C75"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82014380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency 用于摩擦电能量收集接口的双向高压双输入降压变换器，端到端效率达到70.72%
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778018
Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim
{"title":"A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency","authors":"Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim","doi":"10.23919/VLSIC.2019.8778018","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778018","url":null,"abstract":"A bidirectional high-voltage (HV) dual-input (DI) buck converter and a fully integrated maximum power point (MPP) tracker for a triboelectric (TE) energy-harvesting (EH) system are proposed. The proposed MPP tracker carries out the fractional open-circuit voltage (FOCV) method without any external resistor for voltage down conversion. The proposed buck converter regulates two high DC voltages from a triboelectric nanogenerator (TENG) up to 70 V with a single shared inductor. By reducing the capacitance at the switching node, the power conversion efficiency is improved, and the maximum end-to-end efficiency is 70.72%, which is 21.15% higher than prior work.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"7 1","pages":"C326-C327"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76682995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
VLSI Circuits 2019 Friday Forum VLSI电路2019周五论坛
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8778133
{"title":"VLSI Circuits 2019 Friday Forum","authors":"","doi":"10.23919/vlsic.2019.8778133","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8778133","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"149 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75049214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Crystal-Free Single-Chip Micro Mote with Integrated 802.15.4 Compatible Transceiver, sub-mW BLE Compatible Beacon Transmitter, and Cortex M0 集成802.15.4兼容收发器，sub-mW BLE兼容信标发射机和Cortex M0的无晶体单芯片微型Mote
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777971
F. Maksimovic, B. Wheeler, D. Burnett, O. Khan, Sahar M. Mesri, Ioana Suciu, Lydia Lee, A. Moreno, A. Sundararajan, Bob L. Zhou, Rachel Zoll, Andrew Ng, Tengfei Chang, Xavier Vilajosana, T. Watteyne, A. Niknejad, K. Pister
{"title":"A Crystal-Free Single-Chip Micro Mote with Integrated 802.15.4 Compatible Transceiver, sub-mW BLE Compatible Beacon Transmitter, and Cortex M0","authors":"F. Maksimovic, B. Wheeler, D. Burnett, O. Khan, Sahar M. Mesri, Ioana Suciu, Lydia Lee, A. Moreno, A. Sundararajan, Bob L. Zhou, Rachel Zoll, Andrew Ng, Tengfei Chang, Xavier Vilajosana, T. Watteyne, A. Niknejad, K. Pister","doi":"10.23919/VLSIC.2019.8777971","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777971","url":null,"abstract":"We present an 802.15.4 compatible transceiver that operates without any off-chip frequency reference. With integrated Cortex-M0, the chip can also transmit BLE beacons with only three external connections (power, ground, and antenna). The RF transmitter operates with >10% system efficiency at -10 dBm output power from a regulated supply. The entire chip, including the microprocessor, can operate below 1 mW peak power when transmitting. The analog receiver power consumption is 1.03 mW from a 1.5V battery.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"33 1","pages":"C88-C89"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91025065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
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