C. Shiah, C. N. Chang, R. Crisp, C. P. Lin, C. Pan, C. P. Chuang, H. L. Chen, S. Jheng, T. Chang, W. Huang, K. Ting, Rick Dai, W. Huang, B. Rong, Nicky Lu
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A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems
A new breed of Form-Factor-Driven DRAMs offers 80% lower standby power and > 50% IO signal reduction vs. Capacity-Driven commodity DRAM. Command/address/data are multiplexed onto 16 pins and combined with a Serial Control Pin in a Single-Edge-Pinout-Floorplan, providing bus efficiency >98%. Major SOC-DRAM subsystem cost savings are enabled via die size, packaging and PCB area savings using this RPCA. A 100x speedup of array fills using a new Group Write circuit further reduces test cost.
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