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2019 Symposium on VLSI Circuits最新文献

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Spoken vowel classification using synchronization of phase transition nano-oscillators 基于同步相变纳米振荡器的口语元音分类
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777988
S. Dutta, A. Khanna, W. Chakraborty, J. Gomez, S. Joshi, S. Datta
{"title":"Spoken vowel classification using synchronization of phase transition nano-oscillators","authors":"S. Dutta, A. Khanna, W. Chakraborty, J. Gomez, S. Joshi, S. Datta","doi":"10.23919/VLSIC.2019.8777988","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777988","url":null,"abstract":"The paradigm of biologically-inspired computing endows the components of a neural network with dynamical functionality, such as self-oscillations, and harnesses emergent physical phenomena like synchronization, to learn and classify complex temporal patterns. In this work, we exploit the synchronization dynamics of a network of ultra-compact, low power Vanadium dioxide (VO2) based insulator-to-metal phase-transition nano-oscillators (IMT-NO) to classify complex temporal pattern for speech discrimination. We successfully train a network of four capacitively coupled IMTNOs to recognize spoken vowels by tuning their oscillation frequencies electrically according to a real-time learning rule and achieve high recognition rates of 90.5% for spoken vowels. Such an energy-efficient compact hardware with a small number of functional elements are a promising technology option for edge artificial intelligence.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"55 1","pages":"T128-T129"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83885555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI Circuits 2019 Foreword VLSI电路2019前言
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8778137
{"title":"VLSI Circuits 2019 Foreword","authors":"","doi":"10.23919/vlsic.2019.8778137","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8778137","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"68 4","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91475030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[VLSI Circuits 2019 Copyright notice] [VLSI电路2019版权声明]
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8778083
{"title":"[VLSI Circuits 2019 Copyright notice]","authors":"","doi":"10.23919/vlsic.2019.8778083","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8778083","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"69 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88686699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI Circuits 2019 Sunday Workshop VLSI电路2019星期日研讨会
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/vlsic.2019.8777941
{"title":"VLSI Circuits 2019 Sunday Workshop","authors":"","doi":"10.23919/vlsic.2019.8777941","DOIUrl":"https://doi.org/10.23919/vlsic.2019.8777941","url":null,"abstract":"","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"34 7 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89497237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS 一个3.2mW sar辅助CTΔ∑ADC, SNDR为77.5dB, BW为40MHz，采用28nm CMOS
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778176
P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K. Makinwa, L. Breems
{"title":"A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS","authors":"P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K. Makinwa, L. Breems","doi":"10.23919/VLSIC.2019.8778176","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778176","url":null,"abstract":"This paper presents a SAR-assisted Continuous-time Delta-Sigma $( mathrm { CT } Delta Sigma )$ ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of $mathrm { CT } Delta Sigma$ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"26 1","pages":"C230-C231"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74716272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps 一种0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz的带动态电荷泵的偏置双路环结构锁相环
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778061
Zhao Zhang, Guang Zhu, C. Yue
{"title":"A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps","authors":"Zhao Zhang, Guang Zhu, C. Yue","doi":"10.23919/VLSIC.2019.8778061","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778061","url":null,"abstract":"This paper presents an ultra-low-voltage PLL (ULVPLL) with minimum supply voltage at 0.25V. An offset dual-path loop architecture is proposed to relax the current matching requirement in the charge pump (CP) and to mitigate the CP design challenge at such low supply voltage. Two dynamic CP circuits are introduced to lower the design complexity and power consumption. Implemented in 40nm CMOS, the 0.15-1.6GHz ULVPLL is capable of operating under a 0.25-0.4V supply voltage while achieving sub-0.11mW/GHz power efficiency. Measured spur level is -58.3dBc at 0.1GHz offset from 1.6GHz output (under 0.4V supply) and -48.5dBc at 12.5MHz offset from 200MHz output (under 0.25V supply).","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"30 1","pages":"C158-C159"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72570292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array 基于6T SRAM阵列的区域高效和容差内存BNN计算
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778160
Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim
{"title":"Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array","authors":"Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim","doi":"10.23919/VLSIC.2019.8778160","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778160","url":null,"abstract":"We introduce a SRAM-based binary neural network (BNN) hardware which uses a single 6T SRAM cell for XNOR operation for the first time. The cell is 45% smaller than the previous 8T bitcell for XNOR operation. We also propose an in-memory calibration and batch normalization to achieve more reliable operation under the presence of process variation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"5 1","pages":"C118-C119"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81902500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level 一种0.1pJ/b/dB 1.62- 10.8 gb /s视频接口接收机，采用非均匀数据电平进行全自适应均衡
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778084
Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, D. Jeong
{"title":"A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level","authors":"Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, D. Jeong","doi":"10.23919/VLSIC.2019.8778084","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778084","url":null,"abstract":"This paper presents a 65nm CMOS 1.62-to-l0.8Gb/s video interface receiver with fully adaptive equalizers incorporating CTLE and 2-tap DFE. Sign -sign least-mean-squares (SSLMS) algorithm is used for not only the DFE but also the CTLE adaptation to reduce power consumption and extra hardware. An un-even data level is proposed for the optimum locking of the adaptation in the presence of a pre cursor. The receiver achieves BER of 10-12 at 34dB loss channel, occupies 0.174 mm2, and consumes 37.2mW at 10.8Gb/s.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"20 1","pages":"C198-C199"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82760565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 21952-Pixel Multi-Modal CMOS Cellular Sensor Array with 1568-Pixel Parallel Recording and 4-Point Impedance Sensing 具有1568像素并行记录和4点阻抗传感的21952像素多模态CMOS蜂窝传感器阵列
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778043
Doohwan Jung, Jong Seok Park, Gregory V. Junek, S. Grijalva, Sagar R. Kumashi, Adam Wang, Sensen Li, H. Cho, Hua Wang
{"title":"A 21952-Pixel Multi-Modal CMOS Cellular Sensor Array with 1568-Pixel Parallel Recording and 4-Point Impedance Sensing","authors":"Doohwan Jung, Jong Seok Park, Gregory V. Junek, S. Grijalva, Sagar R. Kumashi, Adam Wang, Sensen Li, H. Cho, Hua Wang","doi":"10.23919/VLSIC.2019.8778043","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778043","url":null,"abstract":"This paper presents a fully integrated CMOS multi-modal cellular sensor/stimulator array with 21952 multi-modal pixels, 1568 simultaneous parallel readout channels, 16 μm×16 μm pixel pitch for single cell resolution, and 3.6 mm×1.6 mm tissue-level field-of-view (FoV), achieving high-resolution multi-parametric cellular potential/impedance/optical imaging for holistic cellular characterization and cell-based assays. Moreover, the array system reports the first on-chip true 4-point impedance sensing scheme with 16 parallel impedance sensing channels, which enables precise cellular impedance measurements with aggressively scaled electrodes and large electrode-electrolyte interfacial impedance. The chip also supports concurrent 16-channel 5-bit reconfigurable current-mode cell stimulation. The chip is implemented in a 130 nm low-cost standard CMOS process. Extracellular potentials (700 μV-1.5 mV) from on-chip cultured neonatal rat ventricular myocytes (NRVMs) are successfully measured. With on-chip cultured cardiac fibroblasts, full-chip high-resolution optical images and 4-point impedance mapping precisely capture cell distribution, growth, proliferation, and surface adhesion.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"28 1","pages":"C62-C63"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87055296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Record-High Performance Trantenna Based On Asymmetric Nano-Ring Fet For Polarization-Independent Large-Scale/Real-Time Thz Imaging 基于非对称纳米环场效应晶体管的破纪录高性能太赫兹成像技术
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778116
E. Jang, M. Ryu, R. Patel, S. H. Ahn, H. J. Jeon, K. Han, K. R. Kim
{"title":"Record-High Performance Trantenna Based On Asymmetric Nano-Ring Fet For Polarization-Independent Large-Scale/Real-Time Thz Imaging","authors":"E. Jang, M. Ryu, R. Patel, S. H. Ahn, H. J. Jeon, K. Han, K. R. Kim","doi":"10.23919/VLSIC.2019.8778116","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778116","url":null,"abstract":"We demonstrate a record-high performance monolithic trantenna (transistor-antenna) using 65-nm CMOS foundry in the field of a plasmonic terahertz (THz) detector. By applying ultimate structural asymmetry between source and drain on a ring FET with source diameter $( d_{S})$ scaling from 30 to 0.38 mm, we obtained 180 times more enhanced photoresponse $(Delta u)$ in on-chip THz measurement. Through free-space THz imaging experiments, the conductive drain region of ring FET itself showed a frequency sensitivity with resonance frequency at 0.12 THz in $0.09 sim 0.2$ THz range and polarization-independent imaging results as an isotropic circular antenna. Highlyscalable and feeding line-free monolithic trantenna enables a high-performance THz detector with responsivity of 8.8 kV/W and NEP of 3.36 pW/Hz0.5 at the target frequency.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"56 1","pages":"T160-T161"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90281853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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