A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps

Abstract

This paper presents an ultra-low-voltage PLL (ULVPLL) with minimum supply voltage at 0.25V. An offset dual-path loop architecture is proposed to relax the current matching requirement in the charge pump (CP) and to mitigate the CP design challenge at such low supply voltage. Two dynamic CP circuits are introduced to lower the design complexity and power consumption. Implemented in 40nm CMOS, the 0.15-1.6GHz ULVPLL is capable of operating under a 0.25-0.4V supply voltage while achieving sub-0.11mW/GHz power efficiency. Measured spur level is -58.3dBc at 0.1GHz offset from 1.6GHz output (under 0.4V supply) and -48.5dBc at 12.5MHz offset from 200MHz output (under 0.25V supply).