Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, D. Jeong
{"title":"一种0.1pJ/b/dB 1.62- 10.8 gb /s视频接口接收机,采用非均匀数据电平进行全自适应均衡","authors":"Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, D. Jeong","doi":"10.23919/VLSIC.2019.8778084","DOIUrl":null,"url":null,"abstract":"This paper presents a 65nm CMOS 1.62-to-l0.8Gb/s video interface receiver with fully adaptive equalizers incorporating CTLE and 2-tap DFE. Sign -sign least-mean-squares (SSLMS) algorithm is used for not only the DFE but also the CTLE adaptation to reduce power consumption and extra hardware. An un-even data level is proposed for the optimum locking of the adaptation in the presence of a pre cursor. The receiver achieves BER of 10-12 at 34dB loss channel, occupies 0.174 mm2, and consumes 37.2mW at 10.8Gb/s.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"20 1","pages":"C198-C199"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level\",\"authors\":\"Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, D. Jeong\",\"doi\":\"10.23919/VLSIC.2019.8778084\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 65nm CMOS 1.62-to-l0.8Gb/s video interface receiver with fully adaptive equalizers incorporating CTLE and 2-tap DFE. Sign -sign least-mean-squares (SSLMS) algorithm is used for not only the DFE but also the CTLE adaptation to reduce power consumption and extra hardware. An un-even data level is proposed for the optimum locking of the adaptation in the presence of a pre cursor. The receiver achieves BER of 10-12 at 34dB loss channel, occupies 0.174 mm2, and consumes 37.2mW at 10.8Gb/s.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"20 1\",\"pages\":\"C198-C199\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778084\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778084","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level
This paper presents a 65nm CMOS 1.62-to-l0.8Gb/s video interface receiver with fully adaptive equalizers incorporating CTLE and 2-tap DFE. Sign -sign least-mean-squares (SSLMS) algorithm is used for not only the DFE but also the CTLE adaptation to reduce power consumption and extra hardware. An un-even data level is proposed for the optimum locking of the adaptation in the presence of a pre cursor. The receiver achieves BER of 10-12 at 34dB loss channel, occupies 0.174 mm2, and consumes 37.2mW at 10.8Gb/s.