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2019 Symposium on VLSI Circuits最新文献

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A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca2+-Probe-Based Fluorescence Recording and Electrical Recording 基于荧光记录和电记录的0.7μW/通道Ca2+探针多模态多通道神经活动读出IC
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778042
Taeju Lee, Jee-Ho Park, Ji-Hyoung Cha, Namsun Chou, Doojin Jang, Ji-Hoon Kim, Il-Joo Cho, Seong-Jin Kim, M. Je
{"title":"A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca2+-Probe-Based Fluorescence Recording and Electrical Recording","authors":"Taeju Lee, Jee-Ho Park, Ji-Hyoung Cha, Namsun Chou, Doojin Jang, Ji-Hoon Kim, Il-Joo Cho, Seong-Jin Kim, M. Je","doi":"10.23919/VLSIC.2019.8778042","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778042","url":null,"abstract":"This paper presents a multimodal multichannel neural activity readout IC which can perform not only the electrical recording (ER) but also the fluorescence recording (FR) of neural activity for the cell-type-specific study of heterogeneous neuronal cell populations. The time-based FR circuit senses Ca2+ concentration using Ca2+ probes while the ER circuit acquires action potentials (APs) and local field potentials (LFPs). The IC is fabricated in 0.18μm CMOS. The FR circuit achieves a recording range of 81dB (75pA to 860nA) and consumes the power of 0.7μmW/Ch. The ER circuit achieves the input-referred noise (IRN) of 2.7μm Vrms over the bandwidth (BW) of 10kHz, while consuming the power of 4.9μmW/Ch. The in-vitro measurement is performed for recording Ca2+ concentration and electrical neural signals.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"32 1","pages":"C290-C291"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79565061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping 一种二阶级间增益误差整形的75.8dB-SNDR管道SAR ADC
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778032
Chen-Kai Hsu, Nan Sun
{"title":"A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping","authors":"Chen-Kai Hsu, Nan Sun","doi":"10.23919/VLSIC.2019.8778032","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778032","url":null,"abstract":"This paper presents a low-cost gain error shaping (GES) technique that can substantially suppress the in-band interstage gain error in pipeline ADCs. It works for both closed-loop and open-loop amplification. A prototype ADC with the proposed 2nd-order GES technique in 40nm CMOS achieves 75.8dB SNDR over 12.5MHz BW while operating at 100MS/s and consuming 1.54mW. It achieves 174.9dB Schreier FoM. The GES-related hardware occupies less than 2% of the core area.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"14 1","pages":"C68-C69"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84367585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.74.12 mm3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation 一个1.74.12 mm3完全集成的pH传感器，用于植入式应用，使用差分传感和漂移补偿
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778184
Taewook Kang, Inhee Lee, Sechang Oh, Taekwang Jang, Yejoong Kim, Hyochan Ahn, Gyouho Kim, Se-un Shin, Seokhyeon Jeong, D. Sylvester, D. Blaauw
{"title":"A 1.74.12 mm3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation","authors":"Taewook Kang, Inhee Lee, Sechang Oh, Taekwang Jang, Yejoong Kim, Hyochan Ahn, Gyouho Kim, Se-un Shin, Seokhyeon Jeong, D. Sylvester, D. Blaauw","doi":"10.23919/VLSIC.2019.8778184","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778184","url":null,"abstract":"This paper presents a $1.7 times 4.1 times 2$ mm3 pH sensor that is a fully integrated, stand-alone and implantable system. Instead of a bulky cm size Ag/AgCl electrode, we use a mm-size integrated platinum electrode, and differential sensing using ISFET and REFET pair to compensate for unstable fluid potential. We also propose a drift compensation technique in which the leakage from the source and drain through the gate oxide is canceled, reducing drift $> 100 times $.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"43 1","pages":"C310-C311"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84743802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automotive LIDAR Technology 汽车激光雷达技术
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777993
M. Warren
{"title":"Automotive LIDAR Technology","authors":"M. Warren","doi":"10.23919/VLSIC.2019.8777993","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777993","url":null,"abstract":"LIDAR is an optical analog of radar providing high spatial resolution range information. It is an essential part of the sensor suite for ADAS (Advanced Driver Assistance Systems), and ultimately, autonomous vehicles. Many competing LIDAR designs are being developed by established companies and startup ventures. Although there are no standards, performance and cost expectations for automotive LIDAR are consistent across the automotive industry. Why are there so many different competing designs? We can look at the system requirements and organize the design options around a few key technologies.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"73 1","pages":"C254-C255"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86394022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A 270-Ghz Fully-Integrated Frequency Synthesizer in 65nm CMOS 270ghz全集成频率合成器，65nm CMOS
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777982
Xiaolong Liu, H. Luong
{"title":"A 270-Ghz Fully-Integrated Frequency Synthesizer in 65nm CMOS","authors":"Xiaolong Liu, H. Luong","doi":"10.23919/VLSIC.2019.8777982","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777982","url":null,"abstract":"A fully-integrated sub-THz frequency synthesizer is proposed leveraging an RF sub-sampling PLL (SS-PLL) cascaded with an ILFM-based mm-Wave LO generation chain and a sub-THz mixer for frequency extension. Third-harmonic and fourth-harmonic extraction enhancement methods are proposed for the ILFMx3 and ILFMx4, respectively. A distributed biased technique is proposed to improve the linearity of the magnetic tuning sub-THz ILFMx6. In addition, a frequency tracking loop (FTL) with frequency and amplitude calibration is proposed for the ILFMs. The 65nm CMOS prototype measures a locking range from 61.2-to-100.8GHz, 122.4-to-136.8GHz, and 198.5-to-273.6GHz, phase noise from -79.3dBc/Hz to -95.4dBc/Hz at 1-MHz offset, an integrated jitter from 124fs to 159fs, and an output power of -11dBm and DC-to-RF efficiency of 0.16% at a carrier of 211.4GHz.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"88 1","pages":"C40-C41"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73056575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response 快速瞬态响应的22nm CMOS变化自适应集成计算数字LDO
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778070
K. Z. Ahmed, H. Krishnamurthy, C. Augustine, Xiaosen Liu, Sheldon Weng, K. Ravichandran, J. Tschanz, V. De
{"title":"A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response","authors":"K. Z. Ahmed, H. Krishnamurthy, C. Augustine, Xiaosen Liu, Sheldon Weng, K. Ravichandran, J. Tschanz, V. De","doi":"10.23919/VLSIC.2019.8778070","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778070","url":null,"abstract":"A variation-adaptive computational digital low-dropout regulator (DLDO) uses an event-driven computational controller (CC) to compute the required number of power gates to regulate the output voltage for any load/reference transient. The self-calibrated CC ensures a 2-asynchronous-event-cycle settling time independent of the load/VREF range. Measurements of a 22nm CMOS testchip demonstrate >20X faster settling time and >6X lower droop magnitude than a conventional linear controller (LC) based LDO.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"19 1","pages":"C124-C125"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72744176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm 基于40 nm内存重构的7.3 M输出非零/J稀疏矩阵-矩阵乘法加速器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778147
S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski
{"title":"A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm","authors":"S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski","doi":"10.23919/VLSIC.2019.8778147","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778147","url":null,"abstract":"A Sparse Matrix-Matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40 nm CMOS. On-chip memories are reconfigured as scratchpad or cache and interconnected with synthesizable coalescing crossbars for efficient memory access in each phase of the algorithm. The 2.0 mm $ times 2.6$ mm chip exhibits $12.6 times (8.4times)$ energy efficiency gain, $11.7times (77.6times)$ off-chip bandwidth efficiency gain and$17.1times (36.9times)$ compute density gain against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph based sparse matrices.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"19 1","pages":"C150-C151"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85197358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Recent Progress and Next Directions for Embedded MRAM Technology 嵌入式MRAM技术的最新进展及未来发展方向
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8777932
W. Gallagher, Eric Chien, T. Chiang, Jian-Cheng Huang, Meng-Chun Shih, C. Y. Wang, C. Bair, George Lee, Y. Shih, Chia-Fu Lee, Roger Wang, K. Shen, J. J. Wu, Wayne Wang, H. Chuang
{"title":"Recent Progress and Next Directions for Embedded MRAM Technology","authors":"W. Gallagher, Eric Chien, T. Chiang, Jian-Cheng Huang, Meng-Chun Shih, C. Y. Wang, C. Bair, George Lee, Y. Shih, Chia-Fu Lee, Roger Wang, K. Shen, J. J. Wu, Wayne Wang, H. Chuang","doi":"10.23919/VLSIC.2019.8777932","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777932","url":null,"abstract":"MRAM can play a variety of on-chip memory roles in advanced VLSI technology spanning from high retention, solder-reflow-capable non-volatile memory (NVM) to dense non-volatile or high retention working RAMs. This paper describes results for a solder-reflow-capable MRAM NVM and for extensions that trade off high retention against speed, power, and density.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"1 1","pages":"T190-T191"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82999436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications 一款65nm硅薄盒(SOTB)嵌入式2T-MONOS闪存，实现0.22 pJ/bit读取能量，64mhz接入，适用于物联网应用
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778078
K. Matsubara, Tsutomu Nagasawa, Yoshinobu Kaneda, Hidenori Mitani, Hiroshi Sato, Takashi Iwase, Y. Aoki, K. Maekawa, H. Yamakoshi, T. Ito, H. Kondo, T. Kono
{"title":"A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications","authors":"K. Matsubara, Tsutomu Nagasawa, Yoshinobu Kaneda, Hidenori Mitani, Hiroshi Sato, Takashi Iwase, Y. Aoki, K. Maekawa, H. Yamakoshi, T. Ito, H. Kondo, T. Kono","doi":"10.23919/VLSIC.2019.8778078","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778078","url":null,"abstract":"To expand IoT application ranges, ultra-low active energy operations are expected to edge devices. Especially, read energy reduction in embedded Flash (eFlash) is strongly required to enable real-time sensing with limited energy generated by energy harvesting (EH). In this work, 1.5MB 2T-MONOS eFlash macro is fabricated with 65nm SOTB technology, using low-energy sense amplifier and data transmission circuit techniques which enhance advantages of SOTB devices. The proposed eFlash achieves 0.22 pJ/bit read energy with 64MHz read access, which is low enough to utilize EH technologies as energy sources.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"26 1","pages":"C202-C203"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84151667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices 低功耗边缘器件卷积神经网络加速器中内存计算与传感器处理集成的思考
2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI: 10.23919/VLSIC.2019.8778074
K. Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing Wen, M. Ho, C. Lo, Ren-Shuo Liu, C. Hsieh, Meng-Fan Chang
{"title":"Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices","authors":"K. Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing Wen, M. Ho, C. Lo, Ren-Shuo Liu, C. Hsieh, Meng-Fan Chang","doi":"10.23919/VLSIC.2019.8778074","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778074","url":null,"abstract":"In quest to execute emerging deep learning algorithms at edge devices, developing low-power and low-latency deep learning accelerators (DLAs) have become top priority. To achieve this goal, data processing techniques in sensor and memory utilizing the array structure have drawn much attention. Processing-in-sensor (PIS) solutions could reduce data transfer; computing-in-memory (CIM) macros could reduce memory access and intermediate data movement. We propose a new architecture to integrate PIS and CIM to realize low-power DLA. The advantages of using these techniques and the challenges from system point-of-view are discussed.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"44 1","pages":"T166-T167"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76697225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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