S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski
{"title":"基于40 nm内存重构的7.3 M输出非零/J稀疏矩阵-矩阵乘法加速器","authors":"S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski","doi":"10.23919/VLSIC.2019.8778147","DOIUrl":null,"url":null,"abstract":"A Sparse Matrix-Matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40 nm CMOS. On-chip memories are reconfigured as scratchpad or cache and interconnected with synthesizable coalescing crossbars for efficient memory access in each phase of the algorithm. The 2.0 mm $ \\times 2.6$ mm chip exhibits $12.6 \\times (8.4\\times)$ energy efficiency gain, $11.7\\times (77.6\\times)$ off-chip bandwidth efficiency gain and$17.1\\times (36.9\\times)$ compute density gain against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph based sparse matrices.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"19 1","pages":"C150-C151"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm\",\"authors\":\"S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski\",\"doi\":\"10.23919/VLSIC.2019.8778147\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Sparse Matrix-Matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40 nm CMOS. On-chip memories are reconfigured as scratchpad or cache and interconnected with synthesizable coalescing crossbars for efficient memory access in each phase of the algorithm. The 2.0 mm $ \\\\times 2.6$ mm chip exhibits $12.6 \\\\times (8.4\\\\times)$ energy efficiency gain, $11.7\\\\times (77.6\\\\times)$ off-chip bandwidth efficiency gain and$17.1\\\\times (36.9\\\\times)$ compute density gain against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph based sparse matrices.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"19 1\",\"pages\":\"C150-C151\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778147\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778147","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
采用40 nm CMOS工艺，研制了具有48个异构核和可重构存储器结构的稀疏矩阵-矩阵乘法(SpMM)加速器。片上存储器被重新配置为刮擦板或缓存，并与可合成的聚结交叉条互连，以便在算法的每个阶段有效地访问存储器。2.0 mm × 2.6 mm的芯片在不同的合成和基于真实世界幂律图的稀疏矩阵中，与高端CPU (GPU)相比，具有12.6倍(8.4倍)的能效增益，11.7倍(77.6倍)的片外带宽效率增益和17.1倍(36.9倍)的计算密度增益。
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
A Sparse Matrix-Matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40 nm CMOS. On-chip memories are reconfigured as scratchpad or cache and interconnected with synthesizable coalescing crossbars for efficient memory access in each phase of the algorithm. The 2.0 mm $ \times 2.6$ mm chip exhibits $12.6 \times (8.4\times)$ energy efficiency gain, $11.7\times (77.6\times)$ off-chip bandwidth efficiency gain and$17.1\times (36.9\times)$ compute density gain against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph based sparse matrices.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
