A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response

Abstract

A variation-adaptive computational digital low-dropout regulator (DLDO) uses an event-driven computational controller (CC) to compute the required number of power gates to regulate the output voltage for any load/reference transient. The self-calibrated CC ensures a 2-asynchronous-event-cycle settling time independent of the load/VREF range. Measurements of a 22nm CMOS testchip demonstrate >20X faster settling time and >6X lower droop magnitude than a conventional linear controller (LC) based LDO.