{"title":"一种二阶级间增益误差整形的75.8dB-SNDR管道SAR ADC","authors":"Chen-Kai Hsu, Nan Sun","doi":"10.23919/VLSIC.2019.8778032","DOIUrl":null,"url":null,"abstract":"This paper presents a low-cost gain error shaping (GES) technique that can substantially suppress the in-band interstage gain error in pipeline ADCs. It works for both closed-loop and open-loop amplification. A prototype ADC with the proposed 2nd-order GES technique in 40nm CMOS achieves 75.8dB SNDR over 12.5MHz BW while operating at 100MS/s and consuming 1.54mW. It achieves 174.9dB Schreier FoM. The GES-related hardware occupies less than 2% of the core area.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"14 1","pages":"C68-C69"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping\",\"authors\":\"Chen-Kai Hsu, Nan Sun\",\"doi\":\"10.23919/VLSIC.2019.8778032\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low-cost gain error shaping (GES) technique that can substantially suppress the in-band interstage gain error in pipeline ADCs. It works for both closed-loop and open-loop amplification. A prototype ADC with the proposed 2nd-order GES technique in 40nm CMOS achieves 75.8dB SNDR over 12.5MHz BW while operating at 100MS/s and consuming 1.54mW. It achieves 174.9dB Schreier FoM. The GES-related hardware occupies less than 2% of the core area.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"14 1\",\"pages\":\"C68-C69\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778032\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping
This paper presents a low-cost gain error shaping (GES) technique that can substantially suppress the in-band interstage gain error in pipeline ADCs. It works for both closed-loop and open-loop amplification. A prototype ADC with the proposed 2nd-order GES technique in 40nm CMOS achieves 75.8dB SNDR over 12.5MHz BW while operating at 100MS/s and consuming 1.54mW. It achieves 174.9dB Schreier FoM. The GES-related hardware occupies less than 2% of the core area.
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