一个0.2 - 8 MS/s的10b柔性SAR ADC，实现0.35 - 2.5 fJ/反步，采用自淬动态偏置比较器

2019 Symposium on VLSI Circuits Pub Date : 2019-06-01 DOI:10.23919/VLSIC.2019.8778093

H. S. Bindra, A. Annema, S. Louwsma, B. Nauta

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引用次数: 7

摘要

提出了一种采用自淬动态偏置比较器和自触发异步延迟线的10b柔性SAR ADC。该ADC采用65nm CMOS制造，占地0.04mm2, ENOB > 9bit, SFDR >66dB，采样率为0.2至8MS/s，电源电压分别为0.7V至1.3V, Walden FoM为0.35至2.5fJ/ v-step。关键词:SAR ADC，柔性，瓦尔登曲线，SNDR，动态偏置。

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A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

A 10b flexible SAR ADC is presented incorporating a self-quenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR >66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.

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2019 Symposium on VLSI Circuits

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