Cagla Cakir, A. Chen, Y. Chong, S. Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, M. Bhargava
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A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms
We present a high-performance 6T SRAM architecture equipped with low-power features of late cancel, left-right enable, input-gating, and power-gating. Measurements show that these SRAMs can support CPUs running at 4GHz while offering dynamic power savings of 17% and 6% for the caches and the system respectively and up to 21X static power system savings for the low-power implementation.
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