A 10-MHz 14.3W/mm2 DAB Hysteretic Control Power Converter Achieving 2.5W/247ns Full Load Power Flipping and above 80% Efficiency in 99.9% Power Range for 5G IoTs
{"title":"A 10-MHz 14.3W/mm2 DAB Hysteretic Control Power Converter Achieving 2.5W/247ns Full Load Power Flipping and above 80% Efficiency in 99.9% Power Range for 5G IoTs","authors":"Kang Wei, Bumkil Lee, D. Ma","doi":"10.23919/VLSIC.2019.8778192","DOIUrl":null,"url":null,"abstract":"A double adaptive bound (DAB) hysteretic control power converter is designed for 5G IoTs, which require nanosecond power load flipping and high efficiency across full power range. In response to 1A/3ns load step-up/step-down, it achieves 1% $\\mathrm{t}_{settle}$ of 247ns/387ns, thanks to the DAB control. This is 6× faster than the best of the arts on $0.18 \\mu \\mathrm{m}$ CMOS. A synchronized DCR offset cancellation scheme improves $V_{O}$ regulation accuracy by 10×. As power scales from full to ultra-light load, the controller self-reconfigures to remove redundant controller loss and facilitate adaptive system power delivery. It achieves $\\gt80$% efficiency over 99.9% of 2.5W full power range. Highly efficient design leads to the highest reported chip power density of 14.3W/mm2.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"46 1","pages":"C172-C173"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A double adaptive bound (DAB) hysteretic control power converter is designed for 5G IoTs, which require nanosecond power load flipping and high efficiency across full power range. In response to 1A/3ns load step-up/step-down, it achieves 1% $\mathrm{t}_{settle}$ of 247ns/387ns, thanks to the DAB control. This is 6× faster than the best of the arts on $0.18 \mu \mathrm{m}$ CMOS. A synchronized DCR offset cancellation scheme improves $V_{O}$ regulation accuracy by 10×. As power scales from full to ultra-light load, the controller self-reconfigures to remove redundant controller loss and facilitate adaptive system power delivery. It achieves $\gt80$% efficiency over 99.9% of 2.5W full power range. Highly efficient design leads to the highest reported chip power density of 14.3W/mm2.