A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

Abstract

This paper presents a source-synchronous PAM4 receiver that adopts quarter-rate topology to achieve good bit efficiency and a voltage-controlled delay line (VCDL) in the reference path of a phase-locked loop (PLL) to recover clock and data. With linear quarter-rate samplers, the equalized input signal by two-stage continuous-time linear equalizer (CTLE) is further equalized by 1tap feed forward equalizer (FFE) embedded in the sampler, and then processed by the following power-efficient dynamic latch and CMOS logics. With the VCDL adjusted by a bang-bang phase detector (BBPD) and a charge pump (CP), the output clocks of the four-stage ring oscillator (RO) based PLL have equal phase spacing and track the input data accordingly. The 40-nm CMOS receiver IC achieves error-free operation at 52 Gb/s with a superior bit efficiency of 0.92 pJ/b while compensating for 7.3-dB channel loss at 13 GHz.