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2019 Symposium on VLSI Circuits最新文献

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A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS 923gbps /W、113周期、2盒28nm CMOS高能效AES加速器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778189
Weiwei Shan, A. Fan, Jiaming Xu, Jun Yang, Mingoo Seok
{"title":"A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS","authors":"Weiwei Shan, A. Fan, Jiaming Xu, Jun Yang, Mingoo Seok","doi":"10.23919/VLSIC.2019.8778189","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778189","url":null,"abstract":"An energy-efficient AES hardware accelerator based on 2-Sbox 8-bit datapath is fabricated in 28nm CMOS for IoT and mobile SoC applications. It obtains the smallest encryption cycles of 113 of 8b-AES by 100% utilization of two Sboxes and rearranging data bytes processing order. It also minimizes intermediate data registers (InterReg) to only 40b from 256b by eliminating ShiftRow and MixColumn registers. Along with glitch reduction design of Sbox in native GF $( 2 ^{4})^{2}$ composite-field, it achieves best-in-class efficiency of 257-923 Gbps/W and 28–991Mbps throughput rate at 0.41/0.9V with scalable voltage down to near-threshold.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"28 1","pages":"C236-C237"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86764628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 10mm3 Light-Dose Sensing IoT2 System With 35-To-339nW 10-To-300klx Light-Dose-To-Digital Converter 具有35- 339nw 10- 300klx光剂量-数字转换器的10mm3光剂量传感IoT2系统
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778007
Inhee Lee, Eunseong Moon, Yejoong Kim, J. Phillips, D. Blaauw
{"title":"A 10mm3 Light-Dose Sensing IoT2 System With 35-To-339nW 10-To-300klx Light-Dose-To-Digital Converter","authors":"Inhee Lee, Eunseong Moon, Yejoong Kim, J. Phillips, D. Blaauw","doi":"10.23919/VLSIC.2019.8778007","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778007","url":null,"abstract":"This paper presents a 10mm3 Internet-of-Tiny-Things (IoT2) system that measures light dose using custom photovoltaic cells and a light-dose-to-digital converter (LDDC). The LDDC nulls diode leakage for temperature stability and creates headroom without power overhead by dual forward-biased photovoltaic cells. It also adaptively updates the current mirror ratio and accumulation weighting factor for a low, near-constant power consumption. The system can operate energy-autonomously at $gt 500$ lx light level. The LDDC achieves $mathrm {a}3 sigma $ inaccuracy of ±3.8% and $sigma / mu $ of 2.4% across a wide light intensity range from 10lx to 300klx while consuming only 35 – 339nW.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"42 1","pages":"C180-C181"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87850906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices 全高清60fps CNN超分辨率处理器，基于选择性缓存的移动设备层融合
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778104
Juhyoung Lee, Dongjoo Shin, Jinsu Lee, Jinmook Lee, Sanghoon Kang, H. Yoo
{"title":"A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices","authors":"Juhyoung Lee, Dongjoo Shin, Jinsu Lee, Jinmook Lee, Sanghoon Kang, H. Yoo","doi":"10.23919/VLSIC.2019.8778104","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778104","url":null,"abstract":"A high-throughput CNN super resolution (SR) processor is proposed for memory efficient SR processing. It has three key features: 1) selective caching based layer fusion to minimize external memory access (EMA), 2) memory compaction scheme for smaller on-chip memory footprint, and 3) cyclic ring core architecture to increase the throughput with improved core utilization. As a result, the implemented processor achieves 60 frames-per-second throughput in generating full HD images.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"11 1","pages":"C302-C303"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75826437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An Aptamer-based Electrochemical-Sensing Implant for Continuous Therapeutic- Drug Monitoring in vivo 基于适体体的持续体内治疗药物监测电化学传感植入物
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777991
Jun-Chau Chien, P. Mage, H. Soh, A. Arbabian
{"title":"An Aptamer-based Electrochemical-Sensing Implant for Continuous Therapeutic- Drug Monitoring in vivo","authors":"Jun-Chau Chien, P. Mage, H. Soh, A. Arbabian","doi":"10.23919/VLSIC.2019.8777991","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777991","url":null,"abstract":"This work presents the first fully wireless implant system capable of continuous monitoring of therapeutic drugs in vivo. Electrochemical readout using square-wave voltammetry (SWV) is employed to measure the changes in the drug concentration using redox-labeled structure-switching aptamers. Ultrasound (US) powering and data transmission are employed in the implant for miniaturization, large tissue depth, and high available power. We demonstrate continuous and real-time detection in the human whole blood. Implemented in 65-nm CMOS, the entire implant system operates at 6.64 mW, and measures 140mm3 and 0.24g.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"21 1","pages":"C312-C313"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78263640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation 一种采用1024-APSK调制，数据速率为1.94 Gb/s的3.8 mW极性接收机子采样直接射频-数字转换器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778052
Hechen Wang, Zhan Su, Haoyi Zhao, Yanjie Wang, F. Dai
{"title":"A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation","authors":"Hechen Wang, Zhan Su, Haoyi Zhao, Yanjie Wang, F. Dai","doi":"10.23919/VLSIC.2019.8778052","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778052","url":null,"abstract":"This paper presents a direct RF-to-digital converter (RDC) for polar RX. It consists of a pair of TDCs, an ADC, and a precise sampling position control system. Unlike conventional direct-RF sampling receivers, the RDC samples the input RF signal at baseband rate. It is capable of directly digitizing the phase and amplitude of the received modulated RF signals. It is compatible with a variety of modulations and has advantages of relaxed system requirements on phase noise and linearity when APSK is used. The RDC achieves a max rate of 1.94 GB/s with 1024-APSK at a carrier of 6 GHz, consuming only 3.8mW.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"20 1","pages":"C82-C83"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72850999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range 一种可在667mVpp线性输入范围下实现>100dB SNDR的无放大器无校准SAR ADC
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777944
Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu
{"title":"An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range","authors":"Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu","doi":"10.23919/VLSIC.2019.8777944","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777944","url":null,"abstract":"This work presents a time-multiplexing SAR ADC to support up to 5-lead ECG monitoring with >100dB SNDR per readout channel. Its noise and linearity performance are enhanced by a combination of dual-reference architecture and mismatch error shaping (MES) technique without using amplifiers or calibration, resulting in >106dB SFDR and 109.4dB DR within 250Hz bandwidth (FoMS,DR=178.9dB). The ECG analog front-end (AFE), including 3 DC-coupled instrumentation amplifiers (IAs) and 1 ADC, occupies only 0.48mm2 in 55nm CMOS. Each ECG channel achieves 1μVrms (0.5-250Hz) input-referred noise at a low IA gain of 6V/V with a 667mVpp-diff linear input range.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"63 1","pages":"C70-C71"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81180594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF 一种0.96 PEF的0.6 v无尾逆变叠加放大器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778011
Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, N. Lu, Nan Sun
{"title":"A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF","authors":"Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, N. Lu, Nan Sun","doi":"10.23919/VLSIC.2019.8778011","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778011","url":null,"abstract":"This paper presents a highly power-efficient instrumentation amplifier. It adopts an inverter stacking amplifier (ISA) based 1st-stage that realizes 4x current reuse, thereby greatly reducing the supply current. To boost the power efficiency and enable its robust operation under 0.6V supply, the tail current sources are removed. A high CMRR of 84dB is maintained by combining chopping, closed-loop biasing, and inherent high impedance degeneration. A 3-stage topology with a class-AB last-stage realizes high loop gain and power-efficient dominant-pole compensation. A prototype tail-less ISA in 180nm achieves 1.38uV rms input referred noise (IRN) within 8-kHz BW, while consuming only 2.7uW. This leads to a power efficiency factor (PEF) of 0.96. To authors’ best knowledge, it is the best reported PEF to date.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"107 1","pages":"C144-C145"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77447243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 138Fsrms-Integrated-Jitter and −249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS 基于数字杂散校准技术的28纳米CMOS 138fsms集成抖动和- 249dB-FoM时钟乘法器，杂散为-51dBc
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777937
Yi-An Li, A. Niknejad
{"title":"A 138Fsrms-Integrated-Jitter and −249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS","authors":"Yi-An Li, A. Niknejad","doi":"10.23919/VLSIC.2019.8777937","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777937","url":null,"abstract":"A 3-GHz 8x clock multiplier has been proposed with a jitter performance that is insensitive to frequency drift without a continuous frequency tracking loop (FTL). With the proposed digital calibration techniques, the spurs can be effectively suppressed down to −50.9dBc. Fabricated in 28-nm CMOS technology, this prototype presents an integrated jitter of 138fsrms while consuming 6.5mW from a 1-V/0.8-V supplies and achieves −249dB FoM.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"139 1","pages":"C42-C43"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79872916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications 一种适用于5G应用的26-42 GHz宽带、高效回退和容限驻波CMOS功率放大器架构
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778095
C. R. Chappidi, K. Sengupta
{"title":"A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications","authors":"C. R. Chappidi, K. Sengupta","doi":"10.23919/VLSIC.2019.8778095","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778095","url":null,"abstract":"Future mm-Wave transmitter front-ends will need to operate in an electromagnetically complex environment that are resistant to near-field antenna perturbations (VSWR events) while operating across multiple mmWave frequency bands (28/37/39/42 GHz) and with high efficiency and linearity with spectrally efficient modulation. This is particularly difficult since these parameters (bandwidth, linearity, efficiency, and VSWR tolerance) trade off strongly with each other in a power amplifier (PA). In this paper, we present a PA architecture that exploits mutual load pulling through a multi-port network in a nonlinear fashion to achieve VSWR tolerance while demonstrating Doherty-like operation across 26–42 GHz. The PA designed in 65-nm bulk CMOS generates $mathrm {{P}_{sat}} gt 19$ dBm with $mathrm{PAE _{peak}} gt 20$% across all bands and achieves up to 3.35x and 4.84x enhancement in PAE at back-off power levels of 6 and 9.6 dB over class-A operation. In addition, the PA demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle and supports 64QAM OFDM modulation with 8 Gbps across 28-40GHz.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"31 1","pages":"C22-C23"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78402170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 640×480 Indirect Time-of-Flight CMOS Image Sensor with 4-tap 7-μm Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation Scheme 一种具有4分频7 μm全局快门像素和固定模式相位噪声自补偿方案的640×480间接飞行时间CMOS图像传感器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778090
Min-Sun Keel, Young-Gu Jin, Youngchan Kim, Daeyun Kim, Yeomyung Kim, M. Bae, Bumsik Chung, S. Son, Hogyun Kim, Taemin An, Sungsoo Choi, T. Jung, Yonghun Kwon, Sung-Uk Seo, Sae-Young Kim, Kwanghyuk Bae, Seung-Chul Shin, Myoungoh Ki, Changrok Moon, H. Ryu
{"title":"A 640×480 Indirect Time-of-Flight CMOS Image Sensor with 4-tap 7-μm Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation Scheme","authors":"Min-Sun Keel, Young-Gu Jin, Youngchan Kim, Daeyun Kim, Yeomyung Kim, M. Bae, Bumsik Chung, S. Son, Hogyun Kim, Taemin An, Sungsoo Choi, T. Jung, Yonghun Kwon, Sung-Uk Seo, Sae-Young Kim, Kwanghyuk Bae, Seung-Chul Shin, Myoungoh Ki, Changrok Moon, H. Ryu","doi":"10.23919/VLSIC.2019.8778090","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778090","url":null,"abstract":"${A}640 times 480$ indirect Time-of-Flight (ToF) CMOS image sensor has been designed with 4-tap $7-mu mathrm{m}$ global-shutter pixel in 65-nm back-side illumination (BSI) process. With novel 4tap pixel structure, we achieved motion artifact-free depth map. Column fixed-pattern phase noise (FPPN) is reduced by introducing alternative control of the clock delay propagation path in the photo-gate driver. As a result, motion artifact and column FPPN are not noticeable in the depth map. The proposed ToF sensor shows depth noise less than 0.62% with 940-nm illuminator over the working distance up to 400 cm, and consumes 197 mW for VGA, which is 0.64 pW/pixel.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"11 1","pages":"C258-C259"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86083402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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