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引用次数: 0
摘要
提出了一种无连续频率跟踪环(FTL)的3ghz 8倍时钟乘法器，其抖动性能对频率漂移不敏感。利用所提出的数字校准技术，杂散可以有效地抑制到- 50.9dBc。该原型采用28纳米CMOS技术制造，在1 v /0.8 v电源消耗6.5mW的情况下，具有138fsrms的集成抖动，实现了−249dB的FoM。
A 138Fsrms-Integrated-Jitter and −249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS
A 3-GHz 8x clock multiplier has been proposed with a jitter performance that is insensitive to frequency drift without a continuous frequency tracking loop (FTL). With the proposed digital calibration techniques, the spurs can be effectively suppressed down to −50.9dBc. Fabricated in 28-nm CMOS technology, this prototype presents an integrated jitter of 138fsrms while consuming 6.5mW from a 1-V/0.8-V supplies and achieves −249dB FoM.
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