发布求助
文献互助 智能选刊 最新文献

2019 Symposium on VLSI Circuits最新文献

筛选
英文 中文
A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation 一个0.07mm2 210mW单-1.1 v电源14位10GS/s DAC，同轴平行四边形路由和输出阻抗补偿
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778067
Hung-Yi Huang, T. Kuo
{"title":"A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation","authors":"Hung-Yi Huang, T. Kuo","doi":"10.23919/VLSIC.2019.8778067","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778067","url":null,"abstract":"A DAC with small-size non-cascoded current cells is proposed to achieve small area, low power, high linearity, and wide bandwidth. The proposed concentric parallelogram routing (CPR) reduces mismatch and timing skew among cells. In addition, the proposed output impedance compensation (OIC) remedies the insufficient output impedance of the noncascoded current cells. The DAC, implemented in 28nm CMOS process, achieves $gt64$ dB SFDR over the entire Nyquist bandwidth at 10GS/s while consuming 210mW from a single 1.1V supply. Compared with other state-of-the-art CMOS DACs with resolutions higher than 10bit and Nyquist bandwidths over 3.4GHz, this DAC has an active area of only 0.07mm2 less than 1/12 of the others and the best performance for a commonly-used figure-of-merit (FoM).","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"40 1","pages":"C136-C137"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77554124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing 基于高性能计算的7nm 4GHz Arm®核心coos®芯片设计
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778161
M. Lin, Tze-Chiang Huang, Chien-Chun Tsai, K. Tam, K. Hsieh, Tom Chen, Wen-Hung Huang, J. Hu, Yu-Chi Chen, S. Goel, Chin-Ming Fu, S. Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, F. Lee
{"title":"A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing","authors":"M. Lin, Tze-Chiang Huang, Chien-Chun Tsai, K. Tam, K. Hsieh, Tom Chen, Wen-Hung Huang, J. Hu, Yu-Chi Chen, S. Goel, Chin-Ming Fu, S. Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, F. Lee","doi":"10.23919/VLSIC.2019.8778161","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778161","url":null,"abstract":"A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS®) was implemented in 7nm 15M process. Each SoC chiplet has four Arm® Cortex®-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet connection features a scalable, 0.56pJ/bit power efficiency, 1.6Tb/s/mm2 bandwidth density, and 0.3V Lowvoltage- In-Package-INterCONnect (LIPINCONTM) interface achieving 8Gb/s/pin and 320GB/s bandwidth. Silicon test-chip measurements validate the processor, on-die interconnects and inter-chiplet interface performance. The built-in eye-scan feature shows the inter-chiplet connection achieves 244mV eye-height and 69% UI eye-width.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"196 1","pages":"C28-C29"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88133335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A Low Power Continuous-Time Zoom ADC for Audio Applications 用于音频应用的低功耗连续变焦ADC
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778021
Burak Gönen, Shoubhik Karmakar, R. V. Veldhoven, K. Makinwa
{"title":"A Low Power Continuous-Time Zoom ADC for Audio Applications","authors":"Burak Gönen, Shoubhik Karmakar, R. V. Veldhoven, K. Makinwa","doi":"10.23919/VLSIC.2019.8778021","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778021","url":null,"abstract":"This paper presents a continuous-time (CT) zoom ADC for use in audio applications. Compared to previous zoom ADCs, its input impedance is mainly resistive, making it much easier to drive while still maintaining high energy efficiency. The prototype is fabricated in a 0.16 ×m CMOS process, occupies 0.27 m m2 and achieves 108.5 dB DR, 108.1 dB SNR, 106.4 dB SNDR in a 20 kHz BW, while consuming 618 ×W. This results in a state-of-the-art Schreier FoM of 183.6 dB.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"63 1","pages":"C224-C225"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89840134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2. 一个基于二进制可扩展，8.80 TOPS/W的CNN加速器，具有多核内存处理架构，具有896K突触/mm2。
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778187
S. Okumura, M. Yabuuchi, K. Hijioka, Koichi Nose
{"title":"A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2.","authors":"S. Okumura, M. Yabuuchi, K. Hijioka, Koichi Nose","doi":"10.23919/VLSIC.2019.8778187","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778187","url":null,"abstract":"A Processing-In-Memory (PIM) accelerator with ternary SRAM is proposed for low-power, large-scale deep neural network (DNN) processing. The accelerator consists of Ternary Neural Arithmetic Memory (TNAM) which is capable of bit-scalable MAC (multiply and accumulation) operation in accordance with target accuracy and power limit. An ADC less readout circuits to reduce analog-digital conversion power and a system-level variation avoidance technique utilizing features of TNAM are also proposed. A test chip with large-scale PIM is fabricated and successfully operate convolutional neural networks (CNNs) with 8.8TOPS/W and highest accuracy and area density among recent SRAM-type PIMs are obtained.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"45 1","pages":"C248-C249"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91324698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 64×64 APD-Based ToF Image Sensor with Background Light Suppression up to 200 klx Using In-Pixel Auto-Zeroing and Chopping 基于64×64 apd的ToF图像传感器，背景光抑制高达200 klx，使用像素内自动调零和斩波
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778015
Byungchoul Park, Injun Park, Woojun Choi, Youngcheol Chae
{"title":"A 64×64 APD-Based ToF Image Sensor with Background Light Suppression up to 200 klx Using In-Pixel Auto-Zeroing and Chopping","authors":"Byungchoul Park, Injun Park, Woojun Choi, Youngcheol Chae","doi":"10.23919/VLSIC.2019.8778015","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778015","url":null,"abstract":"This paper presents a time-of-flight (ToF) image sensor for outdoor applications. The sensor employs a gain-modulated avalanche photodiode (APD) that achieves high modulation frequency. The suppression capability of background light is greatly improved up to 200klx by using a combination of in pixel auto-zeroing and chopping. $mathrm{A}64 times 64$ APD-based ToF sensor is fabricated in $mathrm{a}0.11 mu mathrm{m}$ CMOS. It achieves depth ranges from 0.5 to 2 m with 25MHz modulation and from 2 to 20 m with 1.56MHz modulation. For both ranges, it achieves a non-linearity below 0.8% and a precision below 3.4% at a 3D frame rate of 96fps.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"24 1","pages":"C256-C257"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75090752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SNAP: A 1.67 — 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS SNAP:用于16nm CMOS非结构化稀疏深度神经网络推理的1.67 - 21.55TOPS/W稀疏神经加速处理器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778193
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Y. Shao, S. Keckler, Zhengya Zhang
{"title":"SNAP: A 1.67 — 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS","authors":"Jie-Fang Zhang, Ching-En Lee, Chester Liu, Y. Shao, S. Keckler, Zhengya Zhang","doi":"10.23919/VLSIC.2019.8778193","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778193","url":null,"abstract":"A Sparse Neural Acceleration Processor (SNAP) is designed to exploit unstructured sparsity in deep neural networks (DNNs). SNAP uses parallel associative search to discover input pairs to maintain an average 75% hardware utilization. SNAP’s two-level partial sum reduce eliminates access contention and cuts the writeback traffic by $22times$. Through diagonal and row configurations of PE arrays, SNAP supports any CONV and FC layers. A 2.4mm2 16 nm SNAP test chip is measured to achieve a peak effectual efficiency of 21.55TOPS/W (16b) at 0.55V and 260MHz for CONV layers with 10% weight and activation density. Operating on pruned ResNet-50, SNAP achieves 90.98fps at 0.80V and 480MHz, dissipating 348mW.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"14 1","pages":"C306-C307"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90292589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A 76- to 81-GHz, 0.6° rms Phase Error Multi-channel Transmitter with a Novel Phase Detector and Compensation Technique 一种76 ~ 81 ghz、相位误差0.6°rms的多通道发射机，具有一种新型相位检测和补偿技术
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778158
Takeji Fujibayashi, Y. Takeda
{"title":"A 76- to 81-GHz, 0.6° rms Phase Error Multi-channel Transmitter with a Novel Phase Detector and Compensation Technique","authors":"Takeji Fujibayashi, Y. Takeda","doi":"10.23919/VLSIC.2019.8778158","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778158","url":null,"abstract":"A precisely phase controlled transmitter operating in 76- to 81-GHz for the automotive radar application is presented. To achieve accurate phase control, a novel phase detector using 3rd-order distortion is used to compensate the transmitter phase error. The multi-channel transmitter using this detector achieves less than 0.6○ root-mean-square (RMS) phase error in 76- to 81-GHz frequency range. Since the proposed phase detector does not rely on the other TX channels, it’s easy to extend the number of channels. This proposed transmitter is implemented in 65-nm CMOS technology. The phase detector consumes 1.8mW per channel.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"8 1","pages":"C16-C17"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82188223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme 具有近似延迟补偿方案的8nm全数字7.3Gb/s/引脚LPDDR5 PHY
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8777959
Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, J.I. Choi, Shinyoung Yi, Y. Nam, Sang-Won Hwang, Joohyun Lee, Won Lee, Kihwan Seong, Joo-Cheol Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, B. Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko
{"title":"An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme","authors":"Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, J.I. Choi, Shinyoung Yi, Y. Nam, Sang-Won Hwang, Joohyun Lee, Won Lee, Kihwan Seong, Joo-Cheol Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, B. Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko","doi":"10.23919/VLSIC.2019.8777959","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777959","url":null,"abstract":"An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves access valid-window-margin under supply noise without performance penalty. In addition to that, the proposed scheme enables direct DVFS switching due to the voltage variation tolerance with minimized performance penalty. The LPDDR5 PHY in an 8nm technology demonstrated 6.4Gb/s/pin with 0.31UI at 640mV and 7.3Gb/s/pin with 0.25UI at 790mV, respectively. The voltage variation tolerance is measured up to 70mV without memory access black-out.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"20 11-12 1","pages":"C96-C97"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78179190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1–5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM 1-5GHz直接数字射频调制器与嵌入式时间逼近滤波器实现-43dB EVM在1024 QAM
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778115
Shiyu Su, M. Chen
{"title":"A 1–5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM","authors":"Shiyu Su, M. Chen","doi":"10.23919/VLSIC.2019.8778115","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778115","url":null,"abstract":"This paper presents a 1–5GHz direct-digital RF modulator with an embedded time-approximation filter (TAF) to suppress out-of-band noise floor. The proposed TAF technique approximates a FIR impulse response in time domain via a modulated LO waveform, leading to an equivalent RF bandpass filtering during the frequency up-conversion process. The silicon prototype achieves - 43dB EVM for a 10MHz 1024 QAM signal at 2.4GHz with peak stopband noise rejection of > 50 dB.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"137 1","pages":"C20-C21"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79684938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications 液态硅:用于大数据/机器学习应用的具有单片集成ReRAM的非易失性完全可编程内存处理处理器
2019 Symposium on VLSI Circuits Pub Date : 2019-06-09 DOI: 10.23919/VLSIC.2019.8778064
Yue Zha, E. Nowak, J. Li
{"title":"Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications","authors":"Yue Zha, E. Nowak, J. Li","doi":"10.23919/VLSIC.2019.8778064","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778064","url":null,"abstract":"A nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon (L-Si) is demonstrated, which combines the superior programmability of general-purpose computing devices (e.g. FPGA) and the high power efficiency of do-main-specific accelerators. Besides the general computing applications, L-Si is particularly well suited for AI/machine learning and big data applications, which not only pose high computational/memory demand but also evolves rapidly. L-Si is fabricated by monolithically integrating HfO2 resistive RAM on top of commercial 130nm Si CMOS. Our measurement confirmed the fabricated chip operates reliably at low voltage of 650 mV. It achieves 60.9 TOPS/W in performing neural network inferences and 480 GOPS/W in performing content-based similarity search (a key big data application) at nominal voltage supply of 1.2V, showing >$3times $ and ∼$100times $ power efficiency improvement over the state-of-the-art domain-specific CMOS-/RRAM-based accelerators. In addition, it outperforms the latest nonvolatile FPGA in energy efficiency by ∼$3times $ in general compute-intensive applications.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"19 1","pages":"C206-C207"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78273832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信