Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, J.I. Choi, Shinyoung Yi, Y. Nam, Sang-Won Hwang, Joohyun Lee, Won Lee, Kihwan Seong, Joo-Cheol Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, B. Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko
{"title":"具有近似延迟补偿方案的8nm全数字7.3Gb/s/引脚LPDDR5 PHY","authors":"Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, J.I. Choi, Shinyoung Yi, Y. Nam, Sang-Won Hwang, Joohyun Lee, Won Lee, Kihwan Seong, Joo-Cheol Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, B. Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko","doi":"10.23919/VLSIC.2019.8777959","DOIUrl":null,"url":null,"abstract":"An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves access valid-window-margin under supply noise without performance penalty. In addition to that, the proposed scheme enables direct DVFS switching due to the voltage variation tolerance with minimized performance penalty. The LPDDR5 PHY in an 8nm technology demonstrated 6.4Gb/s/pin with 0.31UI at 640mV and 7.3Gb/s/pin with 0.25UI at 790mV, respectively. The voltage variation tolerance is measured up to 70mV without memory access black-out.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"20 11-12 1","pages":"C96-C97"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme\",\"authors\":\"Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, J.I. Choi, Shinyoung Yi, Y. Nam, Sang-Won Hwang, Joohyun Lee, Won Lee, Kihwan Seong, Joo-Cheol Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, B. Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko\",\"doi\":\"10.23919/VLSIC.2019.8777959\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves access valid-window-margin under supply noise without performance penalty. In addition to that, the proposed scheme enables direct DVFS switching due to the voltage variation tolerance with minimized performance penalty. The LPDDR5 PHY in an 8nm technology demonstrated 6.4Gb/s/pin with 0.31UI at 640mV and 7.3Gb/s/pin with 0.25UI at 790mV, respectively. The voltage variation tolerance is measured up to 70mV without memory access black-out.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"20 11-12 1\",\"pages\":\"C96-C97\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8777959\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8777959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme
An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves access valid-window-margin under supply noise without performance penalty. In addition to that, the proposed scheme enables direct DVFS switching due to the voltage variation tolerance with minimized performance penalty. The LPDDR5 PHY in an 8nm technology demonstrated 6.4Gb/s/pin with 0.31UI at 640mV and 7.3Gb/s/pin with 0.25UI at 790mV, respectively. The voltage variation tolerance is measured up to 70mV without memory access black-out.
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