M. Lin, Tze-Chiang Huang, Chien-Chun Tsai, K. Tam, K. Hsieh, Tom Chen, Wen-Hung Huang, J. Hu, Yu-Chi Chen, S. Goel, Chin-Ming Fu, S. Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, F. Lee
{"title":"A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing","authors":"M. Lin, Tze-Chiang Huang, Chien-Chun Tsai, K. Tam, K. Hsieh, Tom Chen, Wen-Hung Huang, J. Hu, Yu-Chi Chen, S. Goel, Chin-Ming Fu, S. Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, F. Lee","doi":"10.23919/VLSIC.2019.8778161","DOIUrl":null,"url":null,"abstract":"A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS®) was implemented in 7nm 15M process. Each SoC chiplet has four Arm® Cortex®-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet connection features a scalable, 0.56pJ/bit power efficiency, 1.6Tb/s/mm2 bandwidth density, and 0.3V Lowvoltage- In-Package-INterCONnect (LIPINCONTM) interface achieving 8Gb/s/pin and 320GB/s bandwidth. Silicon test-chip measurements validate the processor, on-die interconnects and inter-chiplet interface performance. The built-in eye-scan feature shows the inter-chiplet connection achieves 244mV eye-height and 69% UI eye-width.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"196 1","pages":"C28-C29"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 29
Abstract
A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS®) was implemented in 7nm 15M process. Each SoC chiplet has four Arm® Cortex®-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet connection features a scalable, 0.56pJ/bit power efficiency, 1.6Tb/s/mm2 bandwidth density, and 0.3V Lowvoltage- In-Package-INterCONnect (LIPINCONTM) interface achieving 8Gb/s/pin and 320GB/s bandwidth. Silicon test-chip measurements validate the processor, on-die interconnects and inter-chiplet interface performance. The built-in eye-scan feature shows the inter-chiplet connection achieves 244mV eye-height and 69% UI eye-width.
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