A 138Fsrms-Integrated-Jitter and −249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS

Abstract

A 3-GHz 8x clock multiplier has been proposed with a jitter performance that is insensitive to frequency drift without a continuous frequency tracking loop (FTL). With the proposed digital calibration techniques, the spurs can be effectively suppressed down to −50.9dBc. Fabricated in 28-nm CMOS technology, this prototype presents an integrated jitter of 138fsrms while consuming 6.5mW from a 1-V/0.8-V supplies and achieves −249dB FoM.